diff mbox series

[02/11] powerpc/powernv: Add pnv_ioda_pe_iommu_bypass_supported()

Message ID 1572454800-17976-3-git-send-email-arbab@linux.ibm.com (mailing list archive)
State Changes Requested
Headers show
Series powerpv/powernv: Restore pnv_npu_try_dma_set_bypass() | expand

Checks

Context Check Description
snowpatch_ozlabs/apply_patch success Successfully applied on branch powerpc/merge (904ea5d546fe35c670396e4813e15c8b075b69f1)
snowpatch_ozlabs/checkpatch success total: 0 errors, 0 warnings, 0 checks, 32 lines checked

Commit Message

Reza Arbab Oct. 30, 2019, 4:59 p.m. UTC 
This little calculation will be needed in other places. Move it to a
convenience function.

Signed-off-by: Reza Arbab <arbab@linux.ibm.com>
---
 arch/powerpc/platforms/powernv/pci-ioda.c | 8 +++-----
 arch/powerpc/platforms/powernv/pci.h      | 8 ++++++++
 2 files changed, 11 insertions(+), 5 deletions(-)
diff mbox series

Patch

diff --git a/arch/powerpc/platforms/powernv/pci-ioda.c b/arch/powerpc/platforms/powernv/pci-ioda.c
index c28d0d9b7ee0..8849218187d7 100644
--- a/arch/powerpc/platforms/powernv/pci-ioda.c
+++ b/arch/powerpc/platforms/powernv/pci-ioda.c
@@ -1838,11 +1838,9 @@  static bool pnv_pci_ioda_iommu_bypass_supported(struct pci_dev *pdev,
 		return false;
 
 	pe = &phb->ioda.pe_array[pdn->pe_number];
-	if (pe->tce_bypass_enabled) {
-		u64 top = pe->tce_bypass_base + memblock_end_of_DRAM() - 1;
-		if (dma_mask >= top)
-			return true;
-	}
+
+	if (pnv_ioda_pe_iommu_bypass_supported(pe, dma_mask))
+		return true;
 
 	/*
 	 * If the device can't set the TCE bypass bit but still wants
diff --git a/arch/powerpc/platforms/powernv/pci.h b/arch/powerpc/platforms/powernv/pci.h
index f914f0b14e4e..41f7dec3aee5 100644
--- a/arch/powerpc/platforms/powernv/pci.h
+++ b/arch/powerpc/platforms/powernv/pci.h
@@ -4,6 +4,7 @@ 
 
 #include <linux/compiler.h>		/* for __printf */
 #include <linux/iommu.h>
+#include <linux/memblock.h>
 #include <asm/iommu.h>
 #include <asm/msi_bitmap.h>
 
@@ -247,4 +248,11 @@  extern void pnv_pci_setup_iommu_table(struct iommu_table *tbl,
 		void *tce_mem, u64 tce_size,
 		u64 dma_offset, unsigned int page_shift);
 
+static inline bool pnv_ioda_pe_iommu_bypass_supported(struct pnv_ioda_pe *pe,
+						      u64 mask)
+{
+	return pe->tce_bypass_enabled &&
+	       mask >= pe->tce_bypass_base + memblock_end_of_DRAM() - 1;
+}
+
 #endif /* __POWERNV_PCI_H */