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Wed, 30 Oct 2019 17:00:01 +0000 (GMT) Received: from b03ledav002.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id A5A85136066; Wed, 30 Oct 2019 17:00:01 +0000 (GMT) Received: from arbab-laptop.localdomain (unknown [9.53.179.210]) by b03ledav002.gho.boulder.ibm.com (Postfix) with ESMTP; Wed, 30 Oct 2019 17:00:01 +0000 (GMT) Received: by arbab-laptop.localdomain (Postfix, from userid 152845) id 774B24654B0; Wed, 30 Oct 2019 12:00:00 -0500 (CDT) From: Reza Arbab To: linuxppc-dev@lists.ozlabs.org Subject: [PATCH 10/11] powerpc/powernv: Add pnv_phb3_iommu_bypass_supported() Date: Wed, 30 Oct 2019 11:59:59 -0500 Message-Id: <1572454800-17976-11-git-send-email-arbab@linux.ibm.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1572454800-17976-1-git-send-email-arbab@linux.ibm.com> References: <1572454800-17976-1-git-send-email-arbab@linux.ibm.com> X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-10-30_07:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=1 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1908290000 definitions=main-1910300150 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrew Donnellan , Alexey Kardashevskiy , Oliver O'Halloran , Alistair Popple , Paul Mackerras , Thomas Gleixner , Christoph Hellwig Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" Move this code to its own function for reuse. As a side benefit, rearrange the comments and spread things out for readability. Signed-off-by: Reza Arbab --- arch/powerpc/platforms/powernv/pci-ioda.c | 37 +++++++++++++++++++++---------- 1 file changed, 25 insertions(+), 12 deletions(-) diff --git a/arch/powerpc/platforms/powernv/pci-ioda.c b/arch/powerpc/platforms/powernv/pci-ioda.c index 6b932cfc0deb..57e6a43d9a3a 100644 --- a/arch/powerpc/platforms/powernv/pci-ioda.c +++ b/arch/powerpc/platforms/powernv/pci-ioda.c @@ -1826,6 +1826,30 @@ static int pnv_pci_ioda_dma_64bit_bypass(struct pnv_ioda_pe *pe) return -EIO; } +/* + * If the device can't set the TCE bypass bit but still wants + * to access 4GB or more, on PHB3 we can reconfigure TVE#0 to + * bypass the 32-bit region and be usable for 64-bit DMAs. + */ +static bool pnv_phb3_iommu_bypass_supported(struct pnv_ioda_pe *pe, u64 mask) +{ + if (pe->phb->model != PNV_PHB_MODEL_PHB3) + return false; + + /* pe->pdev should be set if it's a single device, pe->pbus if not */ + if (pe->pbus && pe->device_count != 1) + return false; + + if (!(mask >> 32)) + return false; + + /* The device needs to be able to address all of this space. */ + if (mask <= memory_hotplug_max() + (1ULL << 32)) + return false; + + return true; +} + static bool pnv_pci_ioda_iommu_bypass_supported(struct pci_dev *pdev, u64 dma_mask) { @@ -1837,18 +1861,7 @@ static bool pnv_pci_ioda_iommu_bypass_supported(struct pci_dev *pdev, bypass = pnv_ioda_pe_iommu_bypass_supported(pe, dma_mask); - /* - * If the device can't set the TCE bypass bit but still wants - * to access 4GB or more, on PHB3 we can reconfigure TVE#0 to - * bypass the 32-bit region and be usable for 64-bit DMAs. - * The device needs to be able to address all of this space. - */ - if (!bypass && - dma_mask >> 32 && - dma_mask > (memory_hotplug_max() + (1ULL << 32)) && - /* pe->pdev should be set if it's a single device, pe->pbus if not */ - (pe->device_count == 1 || !pe->pbus) && - pe->phb->model == PNV_PHB_MODEL_PHB3) { + if (!bypass && pnv_phb3_iommu_bypass_supported(pe, dma_mask)) { /* Configure the bypass mode */ if (pnv_pci_ioda_dma_64bit_bypass(pe)) return false;