From patchwork Fri Sep 7 19:41:47 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Corentin LABBE X-Patchwork-Id: 967490 Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 426SjX0klzz9s3Z for ; Sat, 8 Sep 2018 05:50:56 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=baylibre.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=baylibre-com.20150623.gappssmtp.com header.i=@baylibre-com.20150623.gappssmtp.com header.b="GRKWfw44"; dkim-atps=neutral Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 426SjW6GwlzF3MT for ; Sat, 8 Sep 2018 05:50:55 +1000 (AEST) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=baylibre.com Authentication-Results: lists.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=baylibre-com.20150623.gappssmtp.com header.i=@baylibre-com.20150623.gappssmtp.com header.b="GRKWfw44"; dkim-atps=neutral X-Original-To: linuxppc-dev@lists.ozlabs.org Delivered-To: linuxppc-dev@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=softfail (mailfrom) smtp.mailfrom=baylibre.com (client-ip=2a00:1450:4864:20::442; helo=mail-wr1-x442.google.com; envelope-from=clabbe@baylibre.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=baylibre.com Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=baylibre-com.20150623.gappssmtp.com header.i=@baylibre-com.20150623.gappssmtp.com header.b="GRKWfw44"; dkim-atps=neutral Received: from mail-wr1-x442.google.com (mail-wr1-x442.google.com [IPv6:2a00:1450:4864:20::442]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 426SWl49XZzF3TV for ; Sat, 8 Sep 2018 05:42:27 +1000 (AEST) Received: by mail-wr1-x442.google.com with SMTP id n2-v6so16033229wrw.7 for ; Fri, 07 Sep 2018 12:42:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=io06vx7Rq8vLff3aAI0vGsa77/DULCcl4h6sMX7yPhA=; b=GRKWfw44LCAUDJ/+WW/sck+S1wTxKgSNInnBo/Q9YaXNphfnGXw06/7J3Ez1L/jTMs UZh2cvjefXMWm8+55e6W/IsZiQi8C1vW58SEd/NW/Bxc2Sj+NrXH8/s+81Eku6bisP96 Ej7fZWV5UIEYHc0kZhGl1kxC+qMSr5SY/5vm7YPmXijyJE+FXtiNXq7FRPTO5saNt7Py gwzM6b6VlgDvekED1sXecoX9dB9t9ccYPakKTd6l4/IUfpHsIGNDVIhW1DPtbpFN0QLT 4xxsO5xk1B/lS5gJd2RnDzOVMoatT78Fq5r2wQXSTDQOMUJ+MwM/oKH2xJYf6B6qOJtm RLBg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=io06vx7Rq8vLff3aAI0vGsa77/DULCcl4h6sMX7yPhA=; b=UhGlJ9QRkMg7Jeln0lsLbN5/o7LzqHl8doWmYXMyAqyvWFqsUfBEgtsf+ZS+is+KH6 FcFbrJlvwQT8KWESoNK3EktpXlSKR359u5aJf3wcrPAgMgBdT+EZ2O9sz8ODweTzAfeW sXEoDh2R3zeY/FNlIinIaNoWTgx6osVpKe87qMt13FnwC1MnTLy5yOVSbLcPNCAI1czI xfsTkwgxUvWqs0bxopPh/m2fjZX7HcggJmGJYmJM4B5y4e6ED+lm4TPUQfG11oYa7txL Us3W3vZR4PRQGMUjTwZQPqAXrmVLaR4EBZ39tTYgPlxgWlSvpTra0dGvBzFRxRSFS0Xb //UQ== X-Gm-Message-State: APzg51AopprCWce84Yjkm8nzA+Ht0k83TLFpw2TgjgYwB7wO3+Jc+ncR 2mekljAQshOTh5/tqHRraCEubA== X-Google-Smtp-Source: ANB0VdZuSObSY2YRl1nDmXGUwpfw2IOIlmMmGYvv/dJXeEr4r3AhROdWB643QaKFXAjh3hdIbQLFQw== X-Received: by 2002:adf:a599:: with SMTP id g25-v6mr7362404wrc.88.1536349344660; Fri, 07 Sep 2018 12:42:24 -0700 (PDT) Received: from localhost.localdomain ([51.15.160.169]) by smtp.googlemail.com with ESMTPSA id y17-v6sm11700133wrh.49.2018.09.07.12.42.23 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 07 Sep 2018 12:42:24 -0700 (PDT) From: Corentin Labbe To: Gilles.Muller@lip6.fr, Julia.Lawall@lip6.fr, agust@denx.de, alexandre.torgue@st.com, alistair@popple.id.au, benh@kernel.crashing.org, carlo@caione.org, davem@davemloft.net, galak@kernel.crashing.org, joabreu@synopsys.com, khilman@baylibre.com, maxime.ripard@bootlin.com, michal.lkml@markovi.net, mpe@ellerman.id.au, mporter@kernel.crashing.org, nicolas.palix@imag.fr, oss@buserror.net, paulus@samba.org, peppe.cavallaro@st.com, tj@kernel.org, vitb@kernel.crashing.org, wens@csie.org Subject: [PATCH 5/5] ata: ahci_sunxi: use xxxsetbits32 functions Date: Fri, 7 Sep 2018 19:41:47 +0000 Message-Id: <1536349307-20714-6-git-send-email-clabbe@baylibre.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1536349307-20714-1-git-send-email-clabbe@baylibre.com> References: <1536349307-20714-1-git-send-email-clabbe@baylibre.com> X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.27 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-ide@vger.kernel.org, linux-sunxi@googlegroups.com, Corentin Labbe , linux-amlogic@lists.infradead.org, linuxppc-dev@lists.ozlabs.org, cocci@systeme.lip6.fr, linux-arm-kernel@lists.infradead.org Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" This patch converts ahci_sunxi to use xxxsetbits32 functions Signed-off-by: Corentin Labbe --- drivers/ata/ahci_sunxi.c | 51 ++++++++++++------------------------------------ 1 file changed, 12 insertions(+), 39 deletions(-) diff --git a/drivers/ata/ahci_sunxi.c b/drivers/ata/ahci_sunxi.c index 911710643305..0799441f1237 100644 --- a/drivers/ata/ahci_sunxi.c +++ b/drivers/ata/ahci_sunxi.c @@ -25,6 +25,7 @@ #include #include #include +#include #include "ahci.h" #define DRV_NAME "ahci-sunxi" @@ -58,34 +59,6 @@ MODULE_PARM_DESC(enable_pmp, #define AHCI_P0PHYCR 0x0178 #define AHCI_P0PHYSR 0x017c -static void sunxi_clrbits(void __iomem *reg, u32 clr_val) -{ - u32 reg_val; - - reg_val = readl(reg); - reg_val &= ~(clr_val); - writel(reg_val, reg); -} - -static void sunxi_setbits(void __iomem *reg, u32 set_val) -{ - u32 reg_val; - - reg_val = readl(reg); - reg_val |= set_val; - writel(reg_val, reg); -} - -static void sunxi_clrsetbits(void __iomem *reg, u32 clr_val, u32 set_val) -{ - u32 reg_val; - - reg_val = readl(reg); - reg_val &= ~(clr_val); - reg_val |= set_val; - writel(reg_val, reg); -} - static u32 sunxi_getbits(void __iomem *reg, u8 mask, u8 shift) { return (readl(reg) >> shift) & mask; @@ -100,22 +73,22 @@ static int ahci_sunxi_phy_init(struct device *dev, void __iomem *reg_base) writel(0, reg_base + AHCI_RWCR); msleep(5); - sunxi_setbits(reg_base + AHCI_PHYCS1R, BIT(19)); - sunxi_clrsetbits(reg_base + AHCI_PHYCS0R, + setbits32(reg_base + AHCI_PHYCS1R, BIT(19)); + clrsetbits32(reg_base + AHCI_PHYCS0R, (0x7 << 24), (0x5 << 24) | BIT(23) | BIT(18)); - sunxi_clrsetbits(reg_base + AHCI_PHYCS1R, + clrsetbits32(reg_base + AHCI_PHYCS1R, (0x3 << 16) | (0x1f << 8) | (0x3 << 6), (0x2 << 16) | (0x6 << 8) | (0x2 << 6)); - sunxi_setbits(reg_base + AHCI_PHYCS1R, BIT(28) | BIT(15)); - sunxi_clrbits(reg_base + AHCI_PHYCS1R, BIT(19)); - sunxi_clrsetbits(reg_base + AHCI_PHYCS0R, + setbits32(reg_base + AHCI_PHYCS1R, BIT(28) | BIT(15)); + clrbits32(reg_base + AHCI_PHYCS1R, BIT(19)); + clrsetbits32(reg_base + AHCI_PHYCS0R, (0x7 << 20), (0x3 << 20)); - sunxi_clrsetbits(reg_base + AHCI_PHYCS2R, + clrsetbits32(reg_base + AHCI_PHYCS2R, (0x1f << 5), (0x19 << 5)); msleep(5); - sunxi_setbits(reg_base + AHCI_PHYCS0R, (0x1 << 19)); + setbits32(reg_base + AHCI_PHYCS0R, (0x1 << 19)); timeout = 250; /* Power up takes aprox 50 us */ do { @@ -130,7 +103,7 @@ static int ahci_sunxi_phy_init(struct device *dev, void __iomem *reg_base) udelay(1); } while (1); - sunxi_setbits(reg_base + AHCI_PHYCS2R, (0x1 << 24)); + setbits32(reg_base + AHCI_PHYCS2R, (0x1 << 24)); timeout = 100; /* Calibration takes aprox 10 us */ do { @@ -158,10 +131,10 @@ static void ahci_sunxi_start_engine(struct ata_port *ap) struct ahci_host_priv *hpriv = ap->host->private_data; /* Setup DMA before DMA start */ - sunxi_clrsetbits(hpriv->mmio + AHCI_P0DMACR, 0x0000ff00, 0x00004400); + clrsetbits32(hpriv->mmio + AHCI_P0DMACR, 0x0000ff00, 0x00004400); /* Start DMA */ - sunxi_setbits(port_mmio + PORT_CMD, PORT_CMD_START); + setbits32(port_mmio + PORT_CMD, PORT_CMD_START); } static const struct ata_port_info ahci_sunxi_port_info = {