From patchwork Wed May 23 07:01:45 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Guo X-Patchwork-Id: 918837 Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 40rPww0QqRz9s02 for ; Wed, 23 May 2018 17:56:48 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="aaxjMhC7"; dkim-atps=neutral Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 40rPwv65g2zDrTs for ; Wed, 23 May 2018 17:56:47 +1000 (AEST) Authentication-Results: lists.ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: lists.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="aaxjMhC7"; dkim-atps=neutral X-Original-To: linuxppc-dev@lists.ozlabs.org Delivered-To: linuxppc-dev@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gmail.com (client-ip=2607:f8b0:400e:c01::244; helo=mail-pl0-x244.google.com; envelope-from=wei.guo.simon@gmail.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="aaxjMhC7"; dkim-atps=neutral Received: from mail-pl0-x244.google.com (mail-pl0-x244.google.com [IPv6:2607:f8b0:400e:c01::244]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 40rPjz52r1zDr2m for ; Wed, 23 May 2018 17:47:19 +1000 (AEST) Received: by mail-pl0-x244.google.com with SMTP id c11-v6so12517548plr.5 for ; Wed, 23 May 2018 00:47:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=MoQt3oKdbE7DibN44o2PeQ1c4XVrhwVnjOkIHD6uyeo=; b=aaxjMhC7ZUdX8WpG32emvr5ieMcgFlhAYHsva7efth2jp+gLfCliKT6Z18osh38mwA PVQCaTY1+fmC2myN38d/D4+93dlgfTA4ZySMWwt5f4HZtgfbAt/kCDKgUvRSVOrYz/+U cscySUti1+alldQTKyQ+/epDHt/6QxMpVnuAaaEnG0kk2Eoad/IP+C6ujby5CQMCpdsX ldwzT6216s+W2h7S+qgp5c9JFzfmbeDOGmlwsHUF0ANsysj7YmLBDy6wxVjoNitgDSox YsU82SgSPFymHH6TKgPEubE9wkz3NjP0EZhg1tU+8k9zJ+rtspCc+6w1toM1BZxK/DQI ZCng== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=MoQt3oKdbE7DibN44o2PeQ1c4XVrhwVnjOkIHD6uyeo=; b=GUikojQm9o44EfTIrwa2pHqcAha7yfmSBsfw1Gx2xNODOyqqJUJWC0ABDNiV8pwWJv kZ+HP4su4ScXGpZuID3l6KSUsQVUfp3N5io0Y+INhlviUmJPXuLeg6pBefRo+aJs7abg /cIFuWolHx/jRGTEBGIOmGLi0paTlJbU9iHfJOaRGvMxUskSSgtGZTrPCwieCLsrfrJG ep79W0wHve22XxOkzdi6T52tS3Ogqwe9aYSZKq1Y1S7I6mKle9lAGl3ZZicClC7GHPDi Q3ltZ1PRts1M8u8QnFFRDzyxXORDG10HGmE7whVSBx5G4EOvZWaFKq3R+uT77/eaUXMS ukaw== X-Gm-Message-State: ALKqPwe+2J+5Il97cNRFwazFCshCLvh4P6aLy5ca390CoobJgYIGotnk Yfg+Qejx3i9uEHTrYEHpvkqEmg== X-Google-Smtp-Source: AB8JxZoG1a7RL2WFnDTHi9BKVJMLA7GVUvifOFAqbkRP/1aqZg0yyyZpV+CSFhALqAWNcM24659B9Q== X-Received: by 2002:a17:902:2848:: with SMTP id e66-v6mr1870165plb.319.1527061637764; Wed, 23 May 2018 00:47:17 -0700 (PDT) Received: from simonLocalRHEL7.cn.ibm.com ([112.73.0.89]) by smtp.gmail.com with ESMTPSA id a4-v6sm39079171pfj.19.2018.05.23.00.47.15 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 23 May 2018 00:47:17 -0700 (PDT) From: wei.guo.simon@gmail.com To: linuxppc-dev@lists.ozlabs.org Subject: [PATCH v4 02/29] powerpc: add TEXASR related macros Date: Wed, 23 May 2018 15:01:45 +0800 Message-Id: <1527058932-7434-3-git-send-email-wei.guo.simon@gmail.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1527058932-7434-1-git-send-email-wei.guo.simon@gmail.com> References: <1527058932-7434-1-git-send-email-wei.guo.simon@gmail.com> X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Simon Guo , kvm-ppc@vger.kernel.org, kvm@vger.kernel.org Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" From: Simon Guo This patches add some macros for CR0/TEXASR bits so that PR KVM TM logic(tbegin./treclaim./tabort.) can make use of them later. Signed-off-by: Simon Guo Reviewed-by: Paul Mackerras --- arch/powerpc/include/asm/reg.h | 32 +++++++++++++++++++++++------ arch/powerpc/platforms/powernv/copy-paste.h | 3 +-- 2 files changed, 27 insertions(+), 8 deletions(-) diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h index 44b2be4..5625684 100644 --- a/arch/powerpc/include/asm/reg.h +++ b/arch/powerpc/include/asm/reg.h @@ -146,6 +146,12 @@ #define MSR_64BIT 0 #endif +/* Condition Register related */ +#define CR0_SHIFT 28 +#define CR0_MASK 0xF +#define CR0_TBEGIN_FAILURE (0x2 << 28) /* 0b0010 */ + + /* Power Management - Processor Stop Status and Control Register Fields */ #define PSSCR_RL_MASK 0x0000000F /* Requested Level */ #define PSSCR_MTL_MASK 0x000000F0 /* Maximum Transition Level */ @@ -239,13 +245,27 @@ #define SPRN_TFIAR 0x81 /* Transaction Failure Inst Addr */ #define SPRN_TEXASR 0x82 /* Transaction EXception & Summary */ #define SPRN_TEXASRU 0x83 /* '' '' '' Upper 32 */ -#define TEXASR_ABORT __MASK(63-31) /* terminated by tabort or treclaim */ -#define TEXASR_SUSP __MASK(63-32) /* tx failed in suspended state */ -#define TEXASR_HV __MASK(63-34) /* MSR[HV] when failure occurred */ -#define TEXASR_PR __MASK(63-35) /* MSR[PR] when failure occurred */ -#define TEXASR_FS __MASK(63-36) /* TEXASR Failure Summary */ -#define TEXASR_EXACT __MASK(63-37) /* TFIAR value is exact */ + +#define TEXASR_FC_LG (63 - 7) /* Failure Code */ +#define TEXASR_AB_LG (63 - 31) /* Abort */ +#define TEXASR_SU_LG (63 - 32) /* Suspend */ +#define TEXASR_HV_LG (63 - 34) /* Hypervisor state*/ +#define TEXASR_PR_LG (63 - 35) /* Privilege level */ +#define TEXASR_FS_LG (63 - 36) /* failure summary */ +#define TEXASR_EX_LG (63 - 37) /* TFIAR exact bit */ +#define TEXASR_ROT_LG (63 - 38) /* ROT bit */ + +#define TEXASR_ABORT __MASK(TEXASR_AB_LG) /* terminated by tabort or treclaim */ +#define TEXASR_SUSP __MASK(TEXASR_SU_LG) /* tx failed in suspended state */ +#define TEXASR_HV __MASK(TEXASR_HV_LG) /* MSR[HV] when failure occurred */ +#define TEXASR_PR __MASK(TEXASR_PR_LG) /* MSR[PR] when failure occurred */ +#define TEXASR_FS __MASK(TEXASR_FS_LG) /* TEXASR Failure Summary */ +#define TEXASR_EXACT __MASK(TEXASR_EX_LG) /* TFIAR value is exact */ +#define TEXASR_ROT __MASK(TEXASR_ROT_LG) +#define TEXASR_FC (ASM_CONST(0xFF) << TEXASR_FC_LG) + #define SPRN_TFHAR 0x80 /* Transaction Failure Handler Addr */ + #define SPRN_TIDR 144 /* Thread ID register */ #define SPRN_CTRLF 0x088 #define SPRN_CTRLT 0x098 diff --git a/arch/powerpc/platforms/powernv/copy-paste.h b/arch/powerpc/platforms/powernv/copy-paste.h index c9a5036..3fa62de 100644 --- a/arch/powerpc/platforms/powernv/copy-paste.h +++ b/arch/powerpc/platforms/powernv/copy-paste.h @@ -7,9 +7,8 @@ * 2 of the License, or (at your option) any later version. */ #include +#include -#define CR0_SHIFT 28 -#define CR0_MASK 0xF /* * Copy/paste instructions: *