From patchwork Wed May 23 07:01:59 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Guo X-Patchwork-Id: 918869 Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 40rQkX30gVz9s2L for ; Wed, 23 May 2018 18:32:52 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="ZViMbsuq"; dkim-atps=neutral Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 40rQkX0VQYzF0dT for ; Wed, 23 May 2018 18:32:52 +1000 (AEST) Authentication-Results: lists.ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: lists.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="ZViMbsuq"; dkim-atps=neutral X-Original-To: linuxppc-dev@lists.ozlabs.org Delivered-To: linuxppc-dev@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gmail.com (client-ip=2607:f8b0:400e:c01::244; helo=mail-pl0-x244.google.com; envelope-from=wei.guo.simon@gmail.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="ZViMbsuq"; dkim-atps=neutral Received: from mail-pl0-x244.google.com (mail-pl0-x244.google.com [IPv6:2607:f8b0:400e:c01::244]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 40rPkl2WM6zDrbm for ; Wed, 23 May 2018 17:47:59 +1000 (AEST) Received: by mail-pl0-x244.google.com with SMTP id n10-v6so12519655plp.0 for ; Wed, 23 May 2018 00:47:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ZB7zpi2XoJt5fLnNQ3hRpNyoThUsIHwZ8V+LkldTJ10=; b=ZViMbsuqPwC+Wl2A25djczK+zfMpsTy3g+awRm9LC01pu0JjAcw45L3T0Zqm+tloUI xK7CPLCH4T4sdUFjwzxthHHAndiBEyVTsH+GF+CGBtrlpJoHMKcqeuxJJheRG+yd9MFS cAdbGj+yLNNrQGmaTLIqDnWQzwxIiPzHgIWW/2wYRxLeTezi3W1jn38Wg01HqpRGmfSI NkMloBM56lb/1SjplTcsPEFBlyltSiCwohUJRGn4n9xhLLXGxBgKMSIofusw+6CA6x35 pPU91ySg3LOFwtbzAHn1dOG8yLSTrDC6WZrAIKdV09o/tEDCqfKwgRCq7VuM6G2q+h+V VBMg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ZB7zpi2XoJt5fLnNQ3hRpNyoThUsIHwZ8V+LkldTJ10=; b=grPXrqkDjoiqu6FE8QeX1vregju3TmY5Qn8gJf39reXCOnZAyNYIlH8Qb4HnA+PjyB 3lyx0p/7mzQlpk+ET9lm45nUwfgcLFOKU/SF7sMPLK9iV5fX6X8WXWuO8zsUR1h3pD1N NwulJ0YT0Rt0eVjbHcCeoVnFz/3gXIP6Z8b7y04whLL8bgqIYEz0yZBtQk4wL0fwIwia +b6dY2x6D3pffJMnTEKPl3XKALTn/lMFWefKbZntM0fqiMn1vmH9XFCGWNWrHQP3P8kZ 7J3ZUeo5eSezId/HwPEqPl7MjkydTYw18Oz+DNN7ru8ewb0fXMXYnTMdPvSd22SRZlxX /q1A== X-Gm-Message-State: ALKqPwdCwAGrv4XyVABgnQGAyIHIByR7Lbdo9SILxbAHLYAoSsMap0/t lkRN1TuwD7Dw6IUxYJ6z59CQNw== X-Google-Smtp-Source: AB8JxZrN0/HUb6dMw3ch9ihJSsWz/Iuu8dk1EKC0PXj00VFRzKUhn7dVoVxEy8j19jbvH8DJdR/hOA== X-Received: by 2002:a17:902:10c:: with SMTP id 12-v6mr1877009plb.252.1527061677408; Wed, 23 May 2018 00:47:57 -0700 (PDT) Received: from simonLocalRHEL7.cn.ibm.com ([112.73.0.89]) by smtp.gmail.com with ESMTPSA id a4-v6sm39079171pfj.19.2018.05.23.00.47.54 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 23 May 2018 00:47:56 -0700 (PDT) From: wei.guo.simon@gmail.com To: linuxppc-dev@lists.ozlabs.org Subject: [PATCH v4 16/29] KVM: PPC: Book3S PR: add math support for PR KVM HTM Date: Wed, 23 May 2018 15:01:59 +0800 Message-Id: <1527058932-7434-17-git-send-email-wei.guo.simon@gmail.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1527058932-7434-1-git-send-email-wei.guo.simon@gmail.com> References: <1527058932-7434-1-git-send-email-wei.guo.simon@gmail.com> X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Simon Guo , kvm-ppc@vger.kernel.org, kvm@vger.kernel.org Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" From: Simon Guo The math registers will be saved into vcpu->arch.fp/vr and corresponding vcpu->arch.fp_tm/vr_tm area. We flush or giveup the math regs into vcpu->arch.fp/vr before saving transaction. After transaction is restored, the math regs will be loaded back into regs. If there is a FP/VEC/VSX unavailable exception during transaction active state, the math checkpoint content might be incorrect and we need to do treclaim./load the correct checkpoint val/trechkpt. sequence to retry the transaction. That will make our solution complicated. To solve this issue, we always make the hardware guest MSR math bits (shadow_msr) consistent with the MSR val which guest sees (kvmppc_get_msr()) when guest msr is with tm enabled. Then all FP/VEC/VSX unavailable exception can be delivered to guest and guest handles the exception by itself. Signed-off-by: Simon Guo --- arch/powerpc/kvm/book3s_pr.c | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/arch/powerpc/kvm/book3s_pr.c b/arch/powerpc/kvm/book3s_pr.c index 226bae7..4b81b3c 100644 --- a/arch/powerpc/kvm/book3s_pr.c +++ b/arch/powerpc/kvm/book3s_pr.c @@ -308,6 +308,28 @@ static inline void kvmppc_restore_tm_sprs(struct kvm_vcpu *vcpu) tm_disable(); } +/* loadup math bits which is enabled at kvmppc_get_msr() but not enabled at + * hardware. + */ +static void kvmppc_handle_lost_math_exts(struct kvm_vcpu *vcpu) +{ + ulong exit_nr; + ulong ext_diff = (kvmppc_get_msr(vcpu) & ~vcpu->arch.guest_owned_ext) & + (MSR_FP | MSR_VEC | MSR_VSX); + + if (!ext_diff) + return; + + if (ext_diff == MSR_FP) + exit_nr = BOOK3S_INTERRUPT_FP_UNAVAIL; + else if (ext_diff == MSR_VEC) + exit_nr = BOOK3S_INTERRUPT_ALTIVEC; + else + exit_nr = BOOK3S_INTERRUPT_VSX; + + kvmppc_handle_ext(vcpu, exit_nr, ext_diff); +} + void kvmppc_save_tm_pr(struct kvm_vcpu *vcpu) { if (!(MSR_TM_ACTIVE(kvmppc_get_msr(vcpu)))) { @@ -315,6 +337,8 @@ void kvmppc_save_tm_pr(struct kvm_vcpu *vcpu) return; } + kvmppc_giveup_ext(vcpu, MSR_VSX); + preempt_disable(); _kvmppc_save_tm_pr(vcpu, mfmsr()); preempt_enable(); @@ -324,12 +348,18 @@ void kvmppc_restore_tm_pr(struct kvm_vcpu *vcpu) { if (!MSR_TM_ACTIVE(kvmppc_get_msr(vcpu))) { kvmppc_restore_tm_sprs(vcpu); + if (kvmppc_get_msr(vcpu) & MSR_TM) + kvmppc_handle_lost_math_exts(vcpu); return; } preempt_disable(); _kvmppc_restore_tm_pr(vcpu, kvmppc_get_msr(vcpu)); preempt_enable(); + + if (kvmppc_get_msr(vcpu) & MSR_TM) + kvmppc_handle_lost_math_exts(vcpu); + } #endif @@ -468,6 +498,11 @@ static void kvmppc_set_msr_pr(struct kvm_vcpu *vcpu, u64 msr) /* Preload FPU if it's enabled */ if (kvmppc_get_msr(vcpu) & MSR_FP) kvmppc_handle_ext(vcpu, BOOK3S_INTERRUPT_FP_UNAVAIL, MSR_FP); + +#ifdef CONFIG_PPC_TRANSACTIONAL_MEM + if (kvmppc_get_msr(vcpu) & MSR_TM) + kvmppc_handle_lost_math_exts(vcpu); +#endif } void kvmppc_set_pvr_pr(struct kvm_vcpu *vcpu, u32 pvr)