From patchwork Wed Apr 25 11:54:43 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Guo X-Patchwork-Id: 904196 Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 40WKGm1BTcz9rxs for ; Wed, 25 Apr 2018 22:28:00 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="CIe1xXbD"; dkim-atps=neutral Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 40WKGl4WcHzF24N for ; Wed, 25 Apr 2018 22:27:59 +1000 (AEST) Authentication-Results: lists.ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: lists.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="CIe1xXbD"; dkim-atps=neutral X-Original-To: linuxppc-dev@lists.ozlabs.org Delivered-To: linuxppc-dev@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gmail.com (client-ip=2607:f8b0:400e:c05::244; helo=mail-pg0-x244.google.com; envelope-from=wei.guo.simon@gmail.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="CIe1xXbD"; dkim-atps=neutral Received: from mail-pg0-x244.google.com (mail-pg0-x244.google.com [IPv6:2607:f8b0:400e:c05::244]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 40WJYF0jzwzF24l for ; Wed, 25 Apr 2018 21:55:29 +1000 (AEST) Received: by mail-pg0-x244.google.com with SMTP id a13so8715933pgu.4 for ; Wed, 25 Apr 2018 04:55:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ok9Zv9WFC/ZyouCJeTkDQC5RHc/aXL1AzstWzGV5Itc=; b=CIe1xXbDrGZOiYzgINg5I84p4q/xsThUZP/ufM8ufa65M8gKo5Tx8uziNRXbXE/LNT k9kRblsMktJ6rzJUknxVjoSdBp+ej/qf2XlDfbOsqNOLmw0rPujOWbCDwBUpO+G9/qe8 ezL1XhjG5kwVI9sxQqPPmJP5S31a4cJ0Z2rRn6Axi/wQi3Ty5PTYirojBRb6UumZxlA5 oKwTF/UnP/CJiefGmH+1fBPcr1tec2g5goaI3lQecsoJVvL7GPx1jvw2k3zIgAB//p5p 5C2p48uFLMHU2i5kICCLwyaxdNzLhhCFwtN5LXQSA9Zl676GxCHslsEnteNvDi8/wxUz Sq7w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ok9Zv9WFC/ZyouCJeTkDQC5RHc/aXL1AzstWzGV5Itc=; b=uXFztxdqjd7904jlHUYgR0TXiCCbQyUzUGk73pxqxMP5+CCpkzM45aCMkNTWCDcZWR 3k1ZSUhphMmiSZHG60Whi6rN3YNhYua/UMD2VroVNOzx+9BnvUmpcGL3C/305ohONkav K+QnI3g2II+gmFWkS/QmZz/sBBYf263t3rNS+EFBY+dQfyUhex0d3JASbhoOpBmcw4+R dWiljudewmmalloq+gwXzX1IyjiQox1vDU6MZGi2oqCC20tKpQhDpWETH2SxF29W5QUy fVz5Z2lI7ZKXEjAD0wsP61qx71EKPnU80DTtyT9oMns9Zh9NYsBq/YIszAadKzcpm/Aj 9BAg== X-Gm-Message-State: ALQs6tAjikxxg16BnsNG1EmkkYQyIMXlA+icK2hFx2f9hjmILIYxHhwN 8bYjBIjHWhwc3BWYfsqtIJI= X-Google-Smtp-Source: AIpwx48w4rKPCoOAhuDUYyiiJWPuN6go7euUSsh646N95/HL32ytJlG8mg5OR7ZMu4tEh6lVVhlcKQ== X-Received: by 10.98.59.24 with SMTP id i24mr27308934pfa.246.1524657327221; Wed, 25 Apr 2018 04:55:27 -0700 (PDT) Received: from simonLocalRHEL7.cn.ibm.com ([112.73.0.87]) by smtp.gmail.com with ESMTPSA id j1sm30912934pgn.69.2018.04.25.04.55.25 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 25 Apr 2018 04:55:26 -0700 (PDT) From: wei.guo.simon@gmail.com To: kvm-ppc@vger.kernel.org Subject: [PATCH 10/11] KVM: PPC: reconstruct LOAD_VMX/STORE_VMX instruction mmio emulation with analyse_intr() input Date: Wed, 25 Apr 2018 19:54:43 +0800 Message-Id: <1524657284-16706-11-git-send-email-wei.guo.simon@gmail.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1524657284-16706-1-git-send-email-wei.guo.simon@gmail.com> References: <1524657284-16706-1-git-send-email-wei.guo.simon@gmail.com> X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Simon Guo , linuxppc-dev@lists.ozlabs.org, kvm@vger.kernel.org Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" From: Simon Guo This patch reconstructs LOAD_VMX/STORE_VMX instruction MMIO emulation with analyse_intr() input. When emulating the store, the VMX reg will need to be flushed so that the right reg val can be retrieved before writing to IO MEM. Suggested-by: Paul Mackerras Signed-off-by: Simon Guo --- arch/powerpc/include/asm/kvm_ppc.h | 1 + arch/powerpc/kvm/emulate_loadstore.c | 73 +++++++++++++++++++++++++----------- arch/powerpc/kvm/powerpc.c | 2 +- 3 files changed, 53 insertions(+), 23 deletions(-) diff --git a/arch/powerpc/include/asm/kvm_ppc.h b/arch/powerpc/include/asm/kvm_ppc.h index b265538..eeb00de 100644 --- a/arch/powerpc/include/asm/kvm_ppc.h +++ b/arch/powerpc/include/asm/kvm_ppc.h @@ -83,6 +83,7 @@ extern int kvmppc_handle_vsx_load(struct kvm_run *run, struct kvm_vcpu *vcpu, int is_default_endian, int mmio_sign_extend); extern int kvmppc_handle_load128_by2x64(struct kvm_run *run, struct kvm_vcpu *vcpu, unsigned int rt, int is_default_endian); +extern int kvmppc_get_vmx_data(struct kvm_vcpu *vcpu, int rs, u64 *val); extern int kvmppc_handle_store128_by2x64(struct kvm_run *run, struct kvm_vcpu *vcpu, unsigned int rs, int is_default_endian); extern int kvmppc_handle_store(struct kvm_run *run, struct kvm_vcpu *vcpu, diff --git a/arch/powerpc/kvm/emulate_loadstore.c b/arch/powerpc/kvm/emulate_loadstore.c index 2dbdf9a..0bfee2f 100644 --- a/arch/powerpc/kvm/emulate_loadstore.c +++ b/arch/powerpc/kvm/emulate_loadstore.c @@ -160,6 +160,27 @@ int kvmppc_emulate_loadstore(struct kvm_vcpu *vcpu) KVM_MMIO_REG_FPR|op.reg, size, 1); break; #endif +#ifdef CONFIG_ALTIVEC + case LOAD_VMX: + if (kvmppc_check_altivec_disabled(vcpu)) + return EMULATE_DONE; + + /* VMX access will need to be size aligned */ + vcpu->arch.vaddr_accessed &= ~((unsigned long)size - 1); + vcpu->arch.paddr_accessed &= ~((unsigned long)size - 1); + + if (size == 16) { + vcpu->arch.mmio_vmx_copy_nums = 2; + emulated = kvmppc_handle_load128_by2x64(run, + vcpu, KVM_MMIO_REG_VMX|op.reg, + 1); + } else if (size <= 8) + emulated = kvmppc_handle_load(run, vcpu, + KVM_MMIO_REG_VMX|op.reg, + size, 1); + + break; +#endif case STORE: if (op.type & UPDATE) { vcpu->arch.mmio_ra = op.update_reg; @@ -197,6 +218,36 @@ int kvmppc_emulate_loadstore(struct kvm_vcpu *vcpu) VCPU_FPR(vcpu, op.reg), size, 1); break; #endif +#ifdef CONFIG_ALTIVEC + case STORE_VMX: + if (kvmppc_check_altivec_disabled(vcpu)) + return EMULATE_DONE; + + /* VMX access will need to be size aligned */ + vcpu->arch.vaddr_accessed &= ~((unsigned long)size - 1); + vcpu->arch.paddr_accessed &= ~((unsigned long)size - 1); + + /* if it is PR KVM, the FP/VEC/VSX registers need to + * be flushed so that kvmppc_handle_store() can read + * actual VMX vals from vcpu->arch. + */ + if (!is_kvmppc_hv_enabled(vcpu->kvm)) + vcpu->kvm->arch.kvm_ops->giveup_ext(vcpu, + MSR_VEC); + + if (size == 16) { + vcpu->arch.mmio_vmx_copy_nums = 2; + emulated = kvmppc_handle_store128_by2x64(run, + vcpu, op.reg, 1); + } else if (size <= 8) { + u64 val; + + kvmppc_get_vmx_data(vcpu, op.reg, &val); + emulated = kvmppc_handle_store(run, vcpu, + val, size, 1); + } + break; +#endif case CACHEOP: /* Do nothing. The guest is performing dcbi because * hardware DMA is not snooped by the dcache, but @@ -354,28 +405,6 @@ int kvmppc_emulate_loadstore(struct kvm_vcpu *vcpu) break; #endif /* CONFIG_VSX */ -#ifdef CONFIG_ALTIVEC - case OP_31_XOP_LVX: - if (kvmppc_check_altivec_disabled(vcpu)) - return EMULATE_DONE; - vcpu->arch.vaddr_accessed &= ~0xFULL; - vcpu->arch.paddr_accessed &= ~0xFULL; - vcpu->arch.mmio_vmx_copy_nums = 2; - emulated = kvmppc_handle_load128_by2x64(run, vcpu, - KVM_MMIO_REG_VMX|rt, 1); - break; - - case OP_31_XOP_STVX: - if (kvmppc_check_altivec_disabled(vcpu)) - return EMULATE_DONE; - vcpu->arch.vaddr_accessed &= ~0xFULL; - vcpu->arch.paddr_accessed &= ~0xFULL; - vcpu->arch.mmio_vmx_copy_nums = 2; - emulated = kvmppc_handle_store128_by2x64(run, vcpu, - rs, 1); - break; -#endif /* CONFIG_ALTIVEC */ - default: emulated = EMULATE_FAIL; break; diff --git a/arch/powerpc/kvm/powerpc.c b/arch/powerpc/kvm/powerpc.c index e724601..000182e 100644 --- a/arch/powerpc/kvm/powerpc.c +++ b/arch/powerpc/kvm/powerpc.c @@ -1408,7 +1408,7 @@ int kvmppc_handle_load128_by2x64(struct kvm_run *run, struct kvm_vcpu *vcpu, return emulated; } -static inline int kvmppc_get_vmx_data(struct kvm_vcpu *vcpu, int rs, u64 *val) +int kvmppc_get_vmx_data(struct kvm_vcpu *vcpu, int rs, u64 *val) { vector128 vrs = VCPU_VSX_VR(vcpu, rs); u32 di;