| Message ID | 1498421326.31581.113.camel@kernel.crashing.org (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | 74e27c6af56fe6898c3c8c451595746a992f0f0f |
| Headers | show |
On Sun, 2017-06-25 at 20:08:46 UTC, Benjamin Herrenschmidt wrote: > From: Michael Neuling <mikey@neuling.org> > > On P9 (Nimbus) DD2 and later, in radix mode, the move to the PID > register will implicitly invalidate the user space ERAT entries > and leave the kernel ones alone. Thus the only thing needed is > an isync() to synchronize this with subsequent uaccess's > > Signed-off-by: Michael Neuling <mikey@neuling.org> > Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Applied to powerpc next, thanks. https://git.kernel.org/powerpc/c/74e27c6af56fe6898c3c8c45159574 cheers
diff --git a/arch/powerpc/mm/mmu_context_book3s64.c b/arch/powerpc/mm/mmu_context_book3s64.c index a3edf813d4..71de2c6d88 100644 --- a/arch/powerpc/mm/mmu_context_book3s64.c +++ b/arch/powerpc/mm/mmu_context_book3s64.c @@ -235,10 +235,15 @@ void destroy_context(struct mm_struct *mm) #ifdef CONFIG_PPC_RADIX_MMU void radix__switch_mmu_context(struct mm_struct *prev, struct mm_struct *next) { - asm volatile("isync": : :"memory"); - mtspr(SPRN_PID, next->context.id); - asm volatile("isync \n" - PPC_SLBIA(0x7) - : : :"memory"); + + if (cpu_has_feature(CPU_FTR_POWER9_DD1)) { + isync(); + mtspr(SPRN_PID, next->context.id); + isync(); + asm volatile(PPC_INVALIDATE_ERAT : : :"memory"); + } else { + mtspr(SPRN_PID, next->context.id); + isync(); + } } #endif