From patchwork Mon Dec 26 08:32:43 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qiang Zhao X-Patchwork-Id: 708760 Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3tnCKP6p41z9svs for ; Mon, 26 Dec 2016 19:46:49 +1100 (AEDT) Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3tnCKP5y7NzDqBM for ; Mon, 26 Dec 2016 19:46:49 +1100 (AEDT) X-Original-To: linuxppc-dev@lists.ozlabs.org Delivered-To: linuxppc-dev@lists.ozlabs.org Received: from NAM01-BN3-obe.outbound.protection.outlook.com (mail-bn3nam01on0054.outbound.protection.outlook.com [104.47.33.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3tnCJ83pqfzDqB8 for ; Mon, 26 Dec 2016 19:45:43 +1100 (AEDT) Received: from BLUPR0301CA0026.namprd03.prod.outlook.com (10.162.113.164) by BN1PR0301MB0738.namprd03.prod.outlook.com (10.160.78.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P384) id 15.1.803.11; Mon, 26 Dec 2016 08:45:38 +0000 Received: from BY2FFO11FD001.protection.gbl (2a01:111:f400:7c0c::176) by BLUPR0301CA0026.outlook.office365.com (2a01:111:e400:5259::36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P384) id 15.1.803.11 via Frontend Transport; Mon, 26 Dec 2016 08:45:38 +0000 Authentication-Results: spf=fail (sender IP is 192.88.168.50) smtp.mailfrom=nxp.com; nxp.com; dkim=none (message not signed) header.d=none; nxp.com; dmarc=fail action=none header.from=nxp.com; nxp.com; dkim=none (message not signed) header.d=none; Received-SPF: Fail (protection.outlook.com: domain of nxp.com does not designate 192.88.168.50 as permitted sender) receiver=protection.outlook.com; client-ip=192.88.168.50; helo=tx30smr01.am.freescale.net; Received: from tx30smr01.am.freescale.net (192.88.168.50) by BY2FFO11FD001.mail.protection.outlook.com (10.1.14.123) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.789.10 via Frontend Transport; Mon, 26 Dec 2016 08:45:37 +0000 Received: from titan.ap.freescale.net ([10.192.208.233]) by tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id uBQ8jWWY023295; Mon, 26 Dec 2016 01:45:33 -0700 From: Zhao Qiang To: , Subject: [Patch V7 1/4] irqchip/qeic: move qeic driver from drivers/soc/fsl/qe Date: Mon, 26 Dec 2016 16:32:43 +0800 Message-ID: <1482741166-33164-1-git-send-email-qiang.zhao@nxp.com> X-Mailer: git-send-email 2.1.0.27.g96db324 X-EOPAttributedMessage: 0 X-Matching-Connectors: 131272155378125001; (91ab9b29-cfa4-454e-5278-08d120cd25b8); () X-Forefront-Antispam-Report: CIP:192.88.168.50; IPV:NLI; CTRY:US; EFV:NLI; SFV:NSPM; SFS:(10009020)(6009001)(7916002)(336005)(39410400002)(39450400003)(39840400002)(39860400002)(39380400002)(39400400002)(39850400002)(2980300002)(1110001)(1109001)(339900001)(199003)(189002)(47776003)(92566002)(104016004)(8676002)(38730400001)(81166006)(5660300001)(36756003)(50226002)(356003)(77096006)(6666003)(4326007)(2906002)(8656002)(626004)(305945005)(8936002)(50986999)(81156014)(48376002)(50466002)(85426001)(5003940100001)(33646002)(97736004)(5001770100001)(189998001)(575784001)(86362001)(106466001)(105606002)(68736007)(7059030)(2004002); DIR:OUT; SFP:1101; SCL:1; SRVR:BN1PR0301MB0738; H:tx30smr01.am.freescale.net; FPR:; SPF:Fail; PTR:InfoDomainNonexistent; A:1; MX:1; LANG:en; X-Microsoft-Exchange-Diagnostics: 1; BY2FFO11FD001; 1:MYvNhnkQ+q+xx7IkedWCDeaoKKwBl7lI3M0/EH2h7tis+Enf0/IDQ/eupJy308rcwpVkMf4r2nnakm/j+GxxgB3xRtauAqJc0La/Upii/NrN0YhMnIFA5mlH+XYImMqJ8pEIIq8jO5Q5IYA5+jrA/UIclfQYVtJYJUhHMkbphTYeMMfxr4+akQ0SPQPWuiobG0k+uA74jTtsZE7SERlZ7QgWZ+uiXr5zaFJOPoTaobh7u/U7eFx/DUx5VHP8R6+HviFaNBSNCciMSW3WhaEQRKmIwKIMfwiDEZ1VVfQVOsKuPHv4Wp+bnIgIjVzxM5ooE7gqDaJ86hNB0yq39vHi+oibO+IuWVRULJqG1BNbyVS2HZBPxg6Fh28CuHO7sUYykYrC71ag6PxvRpREJ5E5Q3hvilb/cHXZOREEqWFe+sc7g57NDveg23UisoQWt5uy0XjTmeyvzkWpNkafNPJTD3sUgBhmqgCW1sqhdRl4RAjsIQ+a5MZ15ChqrhMm4g8yAaNk5IOVGUdKHvgQrgt/FVmcEUR1xUovms253JPY5PXMUFTz92oG5GZXdLLsRveTAMpnB5vCNgyYy+MOKUas4Kwfhvk/TSC0phFe7nuIwhJDHlb0Fpru+yyfdJICQIbNtZmpt20AQyh5xdONi/eCILdi/s9bdIoFqBkNKJaXOPiSMV8VF0CgnwidbJiyQYEfw+FAJz2d0k854jkatmKrrDTi9xNWLRypDL3eAA7NaniWmkzstAWk8qsPUUAClJWw MIME-Version: 1.0 X-MS-Office365-Filtering-Correlation-Id: 31d1b40a-0839-477a-88c9-08d42d6b90ad X-Microsoft-Antispam: UriScan:; BCL:0; PCL:0; RULEID:(22001); SRVR:BN1PR0301MB0738; X-Microsoft-Exchange-Diagnostics: 1; BN1PR0301MB0738; 3:DAL9qGlD4mHc1/yaRNzxnt/HuFdoiN/KyUGwYYy3gIe7JVn1XjPsf4R8fuc3uTwVcMB4KJM1r9vqTICrLJ7Ct7/sLomXVP4Xz9twZMNu3XG2fwGqfVHchzUVVNo1b18aKf6rR+fJxE/2pal9RMOhL8aJorAGoHbN0tS20sA6lSqyZLcncYUsDaA3xNHgQKybdmWZ+XdsVLe198BgxOV+nYXmEbLzr749lisOtXlIDjLujjLvLFGqXv5Y2s6yVdsiZpPOwOKD1FMErwPhmw01+bPEPweHx4V8qluYykHTaKAYpr/p70ba95jMePweShmeAumdeuagwinMLfUhswzqnPqR6T0dBbEBGejNxyt35B6CYafETgdgAdTfLeaRkNZb; 25:gUlhvQGsEYexXwDzN5t3tvKikYwu9p3+Tiurx6/uCxLp77XOdXgWvS5AgBnx/Db786gYmNAjwg2/IeBOlAE/LvebX77iXrB3FoltrjxYymzK01WlYAQKB3w9LLD0puSxhPCodfCBjKjh0RW0r94JhfmZmMDJnABNzuiSYEeYbt/yInlPOsOfwe9xuVzushuCN+HVcB6bviGR/E+0ltlNgSV/2zjtB0gJnoyA5lcbW/NgPR27wZoLA9FZjiaUqMkfOeOU0WdZK+DCwQIq6yP4BQ+poRyeRtOneYbKAGt9MuDGAHmr+LAb1zPTkoTHAxhp7xw7y22G9+5qyGfSauLjOadUibFnkEuQi+PpWIlYB58ktjY2DK6uDdUNHW68rZG81Lw562NuCik4s2+d3P5WSDJrWA5UCwEbsp9h/sxjrIpmfFxcQ1tCPETTJpdZ+kAxaqnZM5VOljMeDaH096DZ3Q== X-Microsoft-Exchange-Diagnostics: 1; BN1PR0301MB0738; 31:LWalnQjD/S0zr0NydZYoY0wzNRbB/CNbOSJ+ffjNVAnKrJMe0J9a9esiVagkJhXo7WTGVuYFgb5iDlGD0fTTX0T17xoJJukD3qxEg415k0cfswMgrT2AaL58/5T2sSX43712GNWt77PVIY7agNJtCTA9L42ScknTwd/4DpPDEZ7myoCzdMkkEBuDk3ZhQSz0BNEQfbMWO9g9eA1lTDRuy1HFKHhGmm2Fm2GOp/C6DidsGa/Gtps0W9xfMVpPz65OqPVvMQ1p2riXjhmM9kpNFQ== X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:(185117386973197)(101931422205132); X-Exchange-Antispam-Report-CFA-Test: BCL:0; PCL:0; RULEID:(6095060)(601004)(2401047)(13024025)(13023025)(13015025)(13017025)(13018025)(8121501046)(5005006)(3002001)(10201501046)(6055026)(6096035)(20161123561025)(20161123559025)(20161123556025)(20161123565025)(20161123563025); SRVR:BN1PR0301MB0738; BCL:0; PCL:0; RULEID:(400006); SRVR:BN1PR0301MB0738; X-Microsoft-Exchange-Diagnostics: 1; BN1PR0301MB0738; 4:rEqFDVckHQE1R9eM4oRvXQVn55KJiFojqZg3TwlEZBAViFq+ar7YWY2cYv9bZdDX6aH3X0hWRr+MfB9q3eWJIKsesEQn/Zj7yvOKkW5z0tQPSE4jPpsTtBieIyuaAo8nXbgVn2j8i2SodMz5hP/BQ+TfmhgRAgwJSVD8PG6PXpwyZsHWgFnha3QXTRJhXfeR4N/2SLOnuAAuocrVnuv6MDT1cIo7c/kSCdw1cTIP5F8trD+v6cWpBw69vJO6VvN6IptxOXMTMx0l9hZ/ErTXJgjgzm0EFS2QWIACm1KD73pdsJ5pv66Nhk0tX5oLP9yH3MZ2G77DglAFI5HIuJLkW1Hh3l2pUIzIfydLuEdeuIRqrDeEWWMY940TpeFBGuPIC9ycMQhrP6HIJpeIkRXdSOs7urOlMVH6SEdWTarhhBxzhUzHHuUDcHchT/A5CPd0xzYFlIGCpzZp7kb+GsdGU1HRMiqS9CGgmzNBDioIiTFnVWxQwn5mL1g7EWKUswuQx0j27CWl9CJ133pRtOXRU0tDcsCvE4vtN7awfMoPLYyL7pd5U6f5K1Q/tVusO/0r9AthO9UALHaqtBv5e8wSC3ZUGv4FFcmBeian7fnUYRjPNMw1I3TL3jbMQ3iGyHSatejBbwqPVd+tXyQl3afNecYzCvbSQAft/r08d3RD3te+6pcxJQvpf+TLVICtCiJoTWBvyfpaekr02vHYlsaKfbtUpbZC8LSOdlfZSujaqUK/dH582OA/EK/LjGD01nAZwadBKUbjbEnuKkBFplV5eg== X-Forefront-PRVS: 016885DD9B X-Microsoft-Exchange-Diagnostics: =?us-ascii?Q?1; BN1PR0301MB0738; 23:2CPxMxzgaNp3UjAfrMdV3fAzZc7xYey9W4NnCY1?= =?us-ascii?Q?q6d+yqUPjg4e7OIsjkYwAQQRvtI3PqpaSzuSZlWlJ2wOTt3m3SqrNz47GdWe?= =?us-ascii?Q?zBMwuwrvJefiO/I1/p7h/jfF1e8sDvc/rOmNwzuV9w2JeHZX9+f6U2fB2Vu/?= =?us-ascii?Q?OyJ+3Fib/9Ri8/DdxCJKujiLy+Cbyvq4TgpNFW/VPrjuyj2/EqXVNT5pzEQ5?= =?us-ascii?Q?FjXTCOxGHh27Ya9wrLG8yFf+hD0yxPr2JTbFy3WR2r3/ybwBZNGMb0nLFPxr?= =?us-ascii?Q?GMIcyEpigSldVmltn4Q1AaXvonWB275u4Ypd0SZFbYn0v0W5fmH2WhWDhldu?= =?us-ascii?Q?BPswfVjsc6Jf6KMkqCzg2XxvwrDK2DZBy0sQGlx2CUUz8kzECEcsA0GFqMxc?= =?us-ascii?Q?U7AABipFIqGhQgbRo/iFE56d97twZx1gm2aDXkITHZ7d/WrvdKOIFnx9XDlp?= =?us-ascii?Q?TskQfX+1INtNjiUdTYLR3Y9rGQZ7yoGnbeA2fNcUUKFOI7hd63/KrbFENgnO?= =?us-ascii?Q?0aI9Lp+C3edBLFqkA0/Tb6ddWTBinTbq/BkBVchEPnBn1CyhIOf2SJAohwKS?= =?us-ascii?Q?GvzcuurfI55nR/x8NKSMmFcoKnFqy57dgGH46Sm08nuFauSCNuIYeL2NJ+pW?= =?us-ascii?Q?nbYwbreLl/D3C4H6XWxpywwpNDq3ozR4sidKJkaLURpqxVCet3smfeWnuMwd?= =?us-ascii?Q?HH4EIYHO2SpwNZFH5FIxm5mKygmWQlMR9ocrLlqDIhf6kh0oSGxMjN1D9G5c?= =?us-ascii?Q?7A70rWstX3VbBY2nAqBI3SbM4cHWV8eCKigWqHat9ytK+ePk3YUeZpLE23+4?= =?us-ascii?Q?Dp9FYud5j8z7/h7t/y05IB6gOrbsUq67CjJlfWCCHaAV34Xz8Q9o1pYKhgcX?= =?us-ascii?Q?D9k0H4wPMRo1RY0sK9fQ+2049fIq1yg3sVvbH4cBXsIIBDXxS64vIXoE4X4O?= =?us-ascii?Q?eHfBvlxd0AnxX4vLo+59uuF2huu1QNbjSWOKdhnUxstA/5Lhc1nVFWHBUdtD?= =?us-ascii?Q?6iVPEYCv3zKSu9PNzLtA6RKbq7ojPeO94nMoepUHFj9wQ+LzZpxNxinTtjj7?= =?us-ascii?Q?DSgwrkcMQRzJr1iWOj8bXdLQfbzj5ypStoCV4mYtntMJLFgDBIGjhvVYhExD?= =?us-ascii?Q?ckKRsYTX4FU73lOJDZLzsCRbf/eUan4oBpnTDSDOArim8/72gzoK5WF85yvx?= =?us-ascii?Q?5tmcIdMNoNnS4IN3o/S+vOHxxjlYneNLLWuHwSCOJUuiSB3RsFodt/itys2D?= =?us-ascii?Q?P70H8ABV/l1jbwTNNdJ0=3D?= X-Microsoft-Exchange-Diagnostics: 1; BN1PR0301MB0738; 6:dn89oZwYmxrX3oAv01dPk4A015IPUKG0RG8hS73/lNc1Cstbga1O7mw+NR08wR63PH04OM+L/EmgFy7Vs3GRW+VgrZBkgEcw1/V7U5xbZxXkDFALKqvkdJpJrYqWkubUYjn7AoxAavxxj4TyAAFR7AsoCJnB0yDco0eVxO2cDpARPzjiWpSZ4WZamW/RscmTLnGRmiBfQpNOrxDU5PFK1kpovsOKl/dpva2k2SD/UfZGACYC3BDDAOGcBgT4OiR7MjCSWzFYnEh+fd4IFekLE7dyKi19d9z3rikJTQVUfKF6+d926D2xGcs0MzWsBKaRBz/u5B6s7xjUHUughXUWhREOrKliLy/c8MTTNc1RNNpVxNqEvZmKwAXo9vzJXC77aLqMncKftMqCJ5u7c8ZiPbnl/H1rGYpC5Y6+yF3oHMJ405LG1vv4/A9oStULz5yo; 5:CXUu4ZtT5nCd354R3PafmWIrPCZ/YVYxjNMxmdddAx7HcgVzGlWFNC8ztsqMUFbern/+bS2ea6SyQwxaPRzL51mFoOQJiVAt1KVzvDOf8DvMybhv1sjW0c2ld4ax86tZrRS1svKqQCX5pK1vbokntxiUAEnYmWoEJEGXEdGTfft1tz2BA+efK/QbfZ9Iq+s0; 24:6nl0LgBG8z+ROcJGubxRAQyN+3wWksVJK85wIY1qf7IhTooBI1O8ZV2ZUQJRA6/C6vfWQhrLefpdiqOqVHz7jGQU191xzvO4ZfR8lozcWG4= SpamDiagnosticOutput: 1:99 SpamDiagnosticMetadata: NSPM X-Microsoft-Exchange-Diagnostics: 1; BN1PR0301MB0738; 7:nLEP9h31ojXCPOMm8MvdprGklcJEMdwq1h5ixNA41LPUCG0kv4XAkzl202QyAvOv1Qlb622m42kwO+kaCPL8pHaeb5LxF2jGA04DO1McPVifXxpXvvPdKzvOl8tLoVDrQ7hK1HpeESuEI8abjp8trab+KmcA1Wxt78xwD9nxbpYQFQ9BmWED7RrS27fR+/Fdygb+xTRivO27ThvheoasmFJ5N3l2tcTCnHXdIKD2a3oTunCvPkfQkOsTEpZD9zf+Jgu+g/OaBsyuwReA2L2TNwf2uLnvxdiVK5Mv5KAPw69Rq1H6K5PmA0hVH3UX/hha4bi/tZwmkFajRldYfvrCJfxRNisTQ4i69PySJ49YeL918rQgCJR1SQIyK+2HQstU+7BpOcbLZ1Dag+t9IsIHak3ItD6CDnM1XBlJ4qqU44NgpaDt0+WAVc8BJs728M+BQcLnulak+GzyxICh20syKg== X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Dec 2016 08:45:37.6252 (UTC) X-MS-Exchange-CrossTenant-Id: 5afe0b00-7697-4969-b663-5eab37d5f47e X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=5afe0b00-7697-4969-b663-5eab37d5f47e; Ip=[192.88.168.50]; Helo=[tx30smr01.am.freescale.net] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN1PR0301MB0738 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-kernel@vger.kernel.org, Zhao Qiang , linuxppc-dev@lists.ozlabs.org, jason@lakedaemon.net, xiaobo.xie@nxp.com Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" move the driver from drivers/soc/fsl/qe to drivers/irqchip, merge qe_ic.h and qe_ic.c into irq-qeic.c. Signed-off-by: Zhao Qiang --- Changes for v2: - modify the subject and commit msg Changes for v3: - merge .h file to .c, rename it with irq-qeic.c Changes for v4: - modify comments Changes for v5: - disable rename detection Changes for v6: - rebase Changes for v7: - na drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-qeic.c | 601 ++++++++++++++++++++++++++++++++++++++++++++ drivers/soc/fsl/qe/Makefile | 2 +- drivers/soc/fsl/qe/qe_ic.c | 512 ------------------------------------- drivers/soc/fsl/qe/qe_ic.h | 103 -------- 5 files changed, 603 insertions(+), 616 deletions(-) create mode 100644 drivers/irqchip/irq-qeic.c delete mode 100644 drivers/soc/fsl/qe/qe_ic.c delete mode 100644 drivers/soc/fsl/qe/qe_ic.h diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile index 4c203b6..face608 100644 --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile @@ -71,3 +71,4 @@ obj-$(CONFIG_MVEBU_ODMI) += irq-mvebu-odmi.o obj-$(CONFIG_LS_SCFG_MSI) += irq-ls-scfg-msi.o obj-$(CONFIG_EZNPS_GIC) += irq-eznps.o obj-$(CONFIG_ARCH_ASPEED) += irq-aspeed-vic.o +obj-$(CONFIG_QUICC_ENGINE) += irq-qeic.o diff --git a/drivers/irqchip/irq-qeic.c b/drivers/irqchip/irq-qeic.c new file mode 100644 index 0000000..48ceded --- /dev/null +++ b/drivers/irqchip/irq-qeic.c @@ -0,0 +1,601 @@ +/* + * drivers/irqchip/irq-qeic.c + * + * Copyright (C) 2016 Freescale Semiconductor, Inc. All rights reserved. + * + * Author: Li Yang + * Based on code from Shlomi Gridish + * + * QUICC ENGINE Interrupt Controller + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define NR_QE_IC_INTS 64 + +/* QE IC registers offset */ +#define QEIC_CICR 0x00 +#define QEIC_CIVEC 0x04 +#define QEIC_CRIPNR 0x08 +#define QEIC_CIPNR 0x0c +#define QEIC_CIPXCC 0x10 +#define QEIC_CIPYCC 0x14 +#define QEIC_CIPWCC 0x18 +#define QEIC_CIPZCC 0x1c +#define QEIC_CIMR 0x20 +#define QEIC_CRIMR 0x24 +#define QEIC_CICNR 0x28 +#define QEIC_CIPRTA 0x30 +#define QEIC_CIPRTB 0x34 +#define QEIC_CRICR 0x3c +#define QEIC_CHIVEC 0x60 + +/* Interrupt priority registers */ +#define CIPCC_SHIFT_PRI0 29 +#define CIPCC_SHIFT_PRI1 26 +#define CIPCC_SHIFT_PRI2 23 +#define CIPCC_SHIFT_PRI3 20 +#define CIPCC_SHIFT_PRI4 13 +#define CIPCC_SHIFT_PRI5 10 +#define CIPCC_SHIFT_PRI6 7 +#define CIPCC_SHIFT_PRI7 4 + +/* CICR priority modes */ +#define CICR_GWCC 0x00040000 +#define CICR_GXCC 0x00020000 +#define CICR_GYCC 0x00010000 +#define CICR_GZCC 0x00080000 +#define CICR_GRTA 0x00200000 +#define CICR_GRTB 0x00400000 +#define CICR_HPIT_SHIFT 8 +#define CICR_HPIT_MASK 0x00000300 +#define CICR_HP_SHIFT 24 +#define CICR_HP_MASK 0x3f000000 + +/* CICNR */ +#define CICNR_WCC1T_SHIFT 20 +#define CICNR_ZCC1T_SHIFT 28 +#define CICNR_YCC1T_SHIFT 12 +#define CICNR_XCC1T_SHIFT 4 + +/* CRICR */ +#define CRICR_RTA1T_SHIFT 20 +#define CRICR_RTB1T_SHIFT 28 + +/* Signal indicator */ +#define SIGNAL_MASK 3 +#define SIGNAL_HIGH 2 +#define SIGNAL_LOW 0 + +struct qe_ic { + /* Control registers offset */ + volatile u32 __iomem *regs; + + /* The remapper for this QEIC */ + struct irq_domain *irqhost; + + /* The "linux" controller struct */ + struct irq_chip hc_irq; + + /* VIRQ numbers of QE high/low irqs */ + unsigned int virq_high; + unsigned int virq_low; +}; + +/* + * QE interrupt controller internal structure + */ +struct qe_ic_info { + /* location of this source at the QIMR register. */ + u32 mask; + + /* Mask register offset */ + u32 mask_reg; + + /* + * for grouped interrupts sources - the interrupt + * code as appears at the group priority register + */ + u8 pri_code; + + /* Group priority register offset */ + u32 pri_reg; +}; + +static DEFINE_RAW_SPINLOCK(qe_ic_lock); + +static struct qe_ic_info qe_ic_info[] = { + [1] = { + .mask = 0x00008000, + .mask_reg = QEIC_CIMR, + .pri_code = 0, + .pri_reg = QEIC_CIPWCC, + }, + [2] = { + .mask = 0x00004000, + .mask_reg = QEIC_CIMR, + .pri_code = 1, + .pri_reg = QEIC_CIPWCC, + }, + [3] = { + .mask = 0x00002000, + .mask_reg = QEIC_CIMR, + .pri_code = 2, + .pri_reg = QEIC_CIPWCC, + }, + [10] = { + .mask = 0x00000040, + .mask_reg = QEIC_CIMR, + .pri_code = 1, + .pri_reg = QEIC_CIPZCC, + }, + [11] = { + .mask = 0x00000020, + .mask_reg = QEIC_CIMR, + .pri_code = 2, + .pri_reg = QEIC_CIPZCC, + }, + [12] = { + .mask = 0x00000010, + .mask_reg = QEIC_CIMR, + .pri_code = 3, + .pri_reg = QEIC_CIPZCC, + }, + [13] = { + .mask = 0x00000008, + .mask_reg = QEIC_CIMR, + .pri_code = 4, + .pri_reg = QEIC_CIPZCC, + }, + [14] = { + .mask = 0x00000004, + .mask_reg = QEIC_CIMR, + .pri_code = 5, + .pri_reg = QEIC_CIPZCC, + }, + [15] = { + .mask = 0x00000002, + .mask_reg = QEIC_CIMR, + .pri_code = 6, + .pri_reg = QEIC_CIPZCC, + }, + [20] = { + .mask = 0x10000000, + .mask_reg = QEIC_CRIMR, + .pri_code = 3, + .pri_reg = QEIC_CIPRTA, + }, + [25] = { + .mask = 0x00800000, + .mask_reg = QEIC_CRIMR, + .pri_code = 0, + .pri_reg = QEIC_CIPRTB, + }, + [26] = { + .mask = 0x00400000, + .mask_reg = QEIC_CRIMR, + .pri_code = 1, + .pri_reg = QEIC_CIPRTB, + }, + [27] = { + .mask = 0x00200000, + .mask_reg = QEIC_CRIMR, + .pri_code = 2, + .pri_reg = QEIC_CIPRTB, + }, + [28] = { + .mask = 0x00100000, + .mask_reg = QEIC_CRIMR, + .pri_code = 3, + .pri_reg = QEIC_CIPRTB, + }, + [32] = { + .mask = 0x80000000, + .mask_reg = QEIC_CIMR, + .pri_code = 0, + .pri_reg = QEIC_CIPXCC, + }, + [33] = { + .mask = 0x40000000, + .mask_reg = QEIC_CIMR, + .pri_code = 1, + .pri_reg = QEIC_CIPXCC, + }, + [34] = { + .mask = 0x20000000, + .mask_reg = QEIC_CIMR, + .pri_code = 2, + .pri_reg = QEIC_CIPXCC, + }, + [35] = { + .mask = 0x10000000, + .mask_reg = QEIC_CIMR, + .pri_code = 3, + .pri_reg = QEIC_CIPXCC, + }, + [36] = { + .mask = 0x08000000, + .mask_reg = QEIC_CIMR, + .pri_code = 4, + .pri_reg = QEIC_CIPXCC, + }, + [40] = { + .mask = 0x00800000, + .mask_reg = QEIC_CIMR, + .pri_code = 0, + .pri_reg = QEIC_CIPYCC, + }, + [41] = { + .mask = 0x00400000, + .mask_reg = QEIC_CIMR, + .pri_code = 1, + .pri_reg = QEIC_CIPYCC, + }, + [42] = { + .mask = 0x00200000, + .mask_reg = QEIC_CIMR, + .pri_code = 2, + .pri_reg = QEIC_CIPYCC, + }, + [43] = { + .mask = 0x00100000, + .mask_reg = QEIC_CIMR, + .pri_code = 3, + .pri_reg = QEIC_CIPYCC, + }, +}; + +static inline u32 qe_ic_read(volatile __be32 __iomem * base, unsigned int reg) +{ + return in_be32(base + (reg >> 2)); +} + +static inline void qe_ic_write(volatile __be32 __iomem * base, unsigned int reg, + u32 value) +{ + out_be32(base + (reg >> 2), value); +} + +static inline struct qe_ic *qe_ic_from_irq(unsigned int virq) +{ + return irq_get_chip_data(virq); +} + +static inline struct qe_ic *qe_ic_from_irq_data(struct irq_data *d) +{ + return irq_data_get_irq_chip_data(d); +} + +static void qe_ic_unmask_irq(struct irq_data *d) +{ + struct qe_ic *qe_ic = qe_ic_from_irq_data(d); + unsigned int src = irqd_to_hwirq(d); + unsigned long flags; + u32 temp; + + raw_spin_lock_irqsave(&qe_ic_lock, flags); + + temp = qe_ic_read(qe_ic->regs, qe_ic_info[src].mask_reg); + qe_ic_write(qe_ic->regs, qe_ic_info[src].mask_reg, + temp | qe_ic_info[src].mask); + + raw_spin_unlock_irqrestore(&qe_ic_lock, flags); +} + +static void qe_ic_mask_irq(struct irq_data *d) +{ + struct qe_ic *qe_ic = qe_ic_from_irq_data(d); + unsigned int src = irqd_to_hwirq(d); + unsigned long flags; + u32 temp; + + raw_spin_lock_irqsave(&qe_ic_lock, flags); + + temp = qe_ic_read(qe_ic->regs, qe_ic_info[src].mask_reg); + qe_ic_write(qe_ic->regs, qe_ic_info[src].mask_reg, + temp & ~qe_ic_info[src].mask); + + /* Flush the above write before enabling interrupts; otherwise, + * spurious interrupts will sometimes happen. To be 100% sure + * that the write has reached the device before interrupts are + * enabled, the mask register would have to be read back; however, + * this is not required for correctness, only to avoid wasting + * time on a large number of spurious interrupts. In testing, + * a sync reduced the observed spurious interrupts to zero. + */ + mb(); + + raw_spin_unlock_irqrestore(&qe_ic_lock, flags); +} + +static struct irq_chip qe_ic_irq_chip = { + .name = "QEIC", + .irq_unmask = qe_ic_unmask_irq, + .irq_mask = qe_ic_mask_irq, + .irq_mask_ack = qe_ic_mask_irq, +}; + +static int qe_ic_host_match(struct irq_domain *h, struct device_node *node, + enum irq_domain_bus_token bus_token) +{ + /* Exact match, unless qe_ic node is NULL */ + struct device_node *of_node = irq_domain_get_of_node(h); + return of_node == NULL || of_node == node; +} + +static int qe_ic_host_map(struct irq_domain *h, unsigned int virq, + irq_hw_number_t hw) +{ + struct qe_ic *qe_ic = h->host_data; + struct irq_chip *chip; + + if (hw >= ARRAY_SIZE(qe_ic_info)) { + pr_err("%s: Invalid hw irq number for QEIC\n", __func__); + return -EINVAL; + } + + if (qe_ic_info[hw].mask == 0) { + printk(KERN_ERR "Can't map reserved IRQ\n"); + return -EINVAL; + } + /* Default chip */ + chip = &qe_ic->hc_irq; + + irq_set_chip_data(virq, qe_ic); + irq_set_status_flags(virq, IRQ_LEVEL); + + irq_set_chip_and_handler(virq, chip, handle_level_irq); + + return 0; +} + +static const struct irq_domain_ops qe_ic_host_ops = { + .match = qe_ic_host_match, + .map = qe_ic_host_map, + .xlate = irq_domain_xlate_onetwocell, +}; + +/* Return an interrupt vector or NO_IRQ if no interrupt is pending. */ +unsigned int qe_ic_get_low_irq(struct qe_ic *qe_ic) +{ + int irq; + + BUG_ON(qe_ic == NULL); + + /* get the interrupt source vector. */ + irq = qe_ic_read(qe_ic->regs, QEIC_CIVEC) >> 26; + + if (irq == 0) + return NO_IRQ; + + return irq_linear_revmap(qe_ic->irqhost, irq); +} + +/* Return an interrupt vector or NO_IRQ if no interrupt is pending. */ +unsigned int qe_ic_get_high_irq(struct qe_ic *qe_ic) +{ + int irq; + + BUG_ON(qe_ic == NULL); + + /* get the interrupt source vector. */ + irq = qe_ic_read(qe_ic->regs, QEIC_CHIVEC) >> 26; + + if (irq == 0) + return NO_IRQ; + + return irq_linear_revmap(qe_ic->irqhost, irq); +} + +void __init qe_ic_init(struct device_node *node, unsigned int flags, + void (*low_handler)(struct irq_desc *desc), + void (*high_handler)(struct irq_desc *desc)) +{ + struct qe_ic *qe_ic; + struct resource res; + u32 temp = 0, ret, high_active = 0; + + ret = of_address_to_resource(node, 0, &res); + if (ret) + return; + + qe_ic = kzalloc(sizeof(*qe_ic), GFP_KERNEL); + if (qe_ic == NULL) + return; + + qe_ic->irqhost = irq_domain_add_linear(node, NR_QE_IC_INTS, + &qe_ic_host_ops, qe_ic); + if (qe_ic->irqhost == NULL) { + kfree(qe_ic); + return; + } + + qe_ic->regs = ioremap(res.start, resource_size(&res)); + + qe_ic->hc_irq = qe_ic_irq_chip; + + qe_ic->virq_high = irq_of_parse_and_map(node, 0); + qe_ic->virq_low = irq_of_parse_and_map(node, 1); + + if (qe_ic->virq_low == NO_IRQ) { + printk(KERN_ERR "Failed to map QE_IC low IRQ\n"); + kfree(qe_ic); + return; + } + + /* default priority scheme is grouped. If spread mode is */ + /* required, configure cicr accordingly. */ + if (flags & QE_IC_SPREADMODE_GRP_W) + temp |= CICR_GWCC; + if (flags & QE_IC_SPREADMODE_GRP_X) + temp |= CICR_GXCC; + if (flags & QE_IC_SPREADMODE_GRP_Y) + temp |= CICR_GYCC; + if (flags & QE_IC_SPREADMODE_GRP_Z) + temp |= CICR_GZCC; + if (flags & QE_IC_SPREADMODE_GRP_RISCA) + temp |= CICR_GRTA; + if (flags & QE_IC_SPREADMODE_GRP_RISCB) + temp |= CICR_GRTB; + + /* choose destination signal for highest priority interrupt */ + if (flags & QE_IC_HIGH_SIGNAL) { + temp |= (SIGNAL_HIGH << CICR_HPIT_SHIFT); + high_active = 1; + } + + qe_ic_write(qe_ic->regs, QEIC_CICR, temp); + + irq_set_handler_data(qe_ic->virq_low, qe_ic); + irq_set_chained_handler(qe_ic->virq_low, low_handler); + + if (qe_ic->virq_high != NO_IRQ && + qe_ic->virq_high != qe_ic->virq_low) { + irq_set_handler_data(qe_ic->virq_high, qe_ic); + irq_set_chained_handler(qe_ic->virq_high, high_handler); + } +} + +void qe_ic_set_highest_priority(unsigned int virq, int high) +{ + struct qe_ic *qe_ic = qe_ic_from_irq(virq); + unsigned int src = virq_to_hw(virq); + u32 temp = 0; + + temp = qe_ic_read(qe_ic->regs, QEIC_CICR); + + temp &= ~CICR_HP_MASK; + temp |= src << CICR_HP_SHIFT; + + temp &= ~CICR_HPIT_MASK; + temp |= (high ? SIGNAL_HIGH : SIGNAL_LOW) << CICR_HPIT_SHIFT; + + qe_ic_write(qe_ic->regs, QEIC_CICR, temp); +} + +/* Set Priority level within its group, from 1 to 8 */ +int qe_ic_set_priority(unsigned int virq, unsigned int priority) +{ + struct qe_ic *qe_ic = qe_ic_from_irq(virq); + unsigned int src = virq_to_hw(virq); + u32 temp; + + if (priority > 8 || priority == 0) + return -EINVAL; + if (WARN_ONCE(src >= ARRAY_SIZE(qe_ic_info), + "%s: Invalid hw irq number for QEIC\n", __func__)) + return -EINVAL; + if (qe_ic_info[src].pri_reg == 0) + return -EINVAL; + + temp = qe_ic_read(qe_ic->regs, qe_ic_info[src].pri_reg); + + if (priority < 4) { + temp &= ~(0x7 << (32 - priority * 3)); + temp |= qe_ic_info[src].pri_code << (32 - priority * 3); + } else { + temp &= ~(0x7 << (24 - priority * 3)); + temp |= qe_ic_info[src].pri_code << (24 - priority * 3); + } + + qe_ic_write(qe_ic->regs, qe_ic_info[src].pri_reg, temp); + + return 0; +} + +/* Set a QE priority to use high irq, only priority 1~2 can use high irq */ +int qe_ic_set_high_priority(unsigned int virq, unsigned int priority, int high) +{ + struct qe_ic *qe_ic = qe_ic_from_irq(virq); + unsigned int src = virq_to_hw(virq); + u32 temp, control_reg = QEIC_CICNR, shift = 0; + + if (priority > 2 || priority == 0) + return -EINVAL; + if (WARN_ONCE(src >= ARRAY_SIZE(qe_ic_info), + "%s: Invalid hw irq number for QEIC\n", __func__)) + return -EINVAL; + + switch (qe_ic_info[src].pri_reg) { + case QEIC_CIPZCC: + shift = CICNR_ZCC1T_SHIFT; + break; + case QEIC_CIPWCC: + shift = CICNR_WCC1T_SHIFT; + break; + case QEIC_CIPYCC: + shift = CICNR_YCC1T_SHIFT; + break; + case QEIC_CIPXCC: + shift = CICNR_XCC1T_SHIFT; + break; + case QEIC_CIPRTA: + shift = CRICR_RTA1T_SHIFT; + control_reg = QEIC_CRICR; + break; + case QEIC_CIPRTB: + shift = CRICR_RTB1T_SHIFT; + control_reg = QEIC_CRICR; + break; + default: + return -EINVAL; + } + + shift += (2 - priority) * 2; + temp = qe_ic_read(qe_ic->regs, control_reg); + temp &= ~(SIGNAL_MASK << shift); + temp |= (high ? SIGNAL_HIGH : SIGNAL_LOW) << shift; + qe_ic_write(qe_ic->regs, control_reg, temp); + + return 0; +} + +static struct bus_type qe_ic_subsys = { + .name = "qe_ic", + .dev_name = "qe_ic", +}; + +static struct device device_qe_ic = { + .id = 0, + .bus = &qe_ic_subsys, +}; + +static int __init init_qe_ic_sysfs(void) +{ + int rc; + + printk(KERN_DEBUG "Registering qe_ic with sysfs...\n"); + + rc = subsys_system_register(&qe_ic_subsys, NULL); + if (rc) { + printk(KERN_ERR "Failed registering qe_ic sys class\n"); + return -ENODEV; + } + rc = device_register(&device_qe_ic); + if (rc) { + printk(KERN_ERR "Failed registering qe_ic sys device\n"); + return -ENODEV; + } + return 0; +} + +subsys_initcall(init_qe_ic_sysfs); diff --git a/drivers/soc/fsl/qe/Makefile b/drivers/soc/fsl/qe/Makefile index 2031d38..51e4726 100644 --- a/drivers/soc/fsl/qe/Makefile +++ b/drivers/soc/fsl/qe/Makefile @@ -1,7 +1,7 @@ # # Makefile for the linux ppc-specific parts of QE # -obj-$(CONFIG_QUICC_ENGINE)+= qe.o qe_common.o qe_ic.o qe_io.o +obj-$(CONFIG_QUICC_ENGINE)+= qe.o qe_common.o qe_io.o obj-$(CONFIG_CPM) += qe_common.o obj-$(CONFIG_UCC) += ucc.o obj-$(CONFIG_UCC_SLOW) += ucc_slow.o diff --git a/drivers/soc/fsl/qe/qe_ic.c b/drivers/soc/fsl/qe/qe_ic.c deleted file mode 100644 index ec2ca86..0000000 --- a/drivers/soc/fsl/qe/qe_ic.c +++ /dev/null @@ -1,512 +0,0 @@ -/* - * arch/powerpc/sysdev/qe_lib/qe_ic.c - * - * Copyright (C) 2006 Freescale Semiconductor, Inc. All rights reserved. - * - * Author: Li Yang - * Based on code from Shlomi Gridish - * - * QUICC ENGINE Interrupt Controller - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "qe_ic.h" - -static DEFINE_RAW_SPINLOCK(qe_ic_lock); - -static struct qe_ic_info qe_ic_info[] = { - [1] = { - .mask = 0x00008000, - .mask_reg = QEIC_CIMR, - .pri_code = 0, - .pri_reg = QEIC_CIPWCC, - }, - [2] = { - .mask = 0x00004000, - .mask_reg = QEIC_CIMR, - .pri_code = 1, - .pri_reg = QEIC_CIPWCC, - }, - [3] = { - .mask = 0x00002000, - .mask_reg = QEIC_CIMR, - .pri_code = 2, - .pri_reg = QEIC_CIPWCC, - }, - [10] = { - .mask = 0x00000040, - .mask_reg = QEIC_CIMR, - .pri_code = 1, - .pri_reg = QEIC_CIPZCC, - }, - [11] = { - .mask = 0x00000020, - .mask_reg = QEIC_CIMR, - .pri_code = 2, - .pri_reg = QEIC_CIPZCC, - }, - [12] = { - .mask = 0x00000010, - .mask_reg = QEIC_CIMR, - .pri_code = 3, - .pri_reg = QEIC_CIPZCC, - }, - [13] = { - .mask = 0x00000008, - .mask_reg = QEIC_CIMR, - .pri_code = 4, - .pri_reg = QEIC_CIPZCC, - }, - [14] = { - .mask = 0x00000004, - .mask_reg = QEIC_CIMR, - .pri_code = 5, - .pri_reg = QEIC_CIPZCC, - }, - [15] = { - .mask = 0x00000002, - .mask_reg = QEIC_CIMR, - .pri_code = 6, - .pri_reg = QEIC_CIPZCC, - }, - [20] = { - .mask = 0x10000000, - .mask_reg = QEIC_CRIMR, - .pri_code = 3, - .pri_reg = QEIC_CIPRTA, - }, - [25] = { - .mask = 0x00800000, - .mask_reg = QEIC_CRIMR, - .pri_code = 0, - .pri_reg = QEIC_CIPRTB, - }, - [26] = { - .mask = 0x00400000, - .mask_reg = QEIC_CRIMR, - .pri_code = 1, - .pri_reg = QEIC_CIPRTB, - }, - [27] = { - .mask = 0x00200000, - .mask_reg = QEIC_CRIMR, - .pri_code = 2, - .pri_reg = QEIC_CIPRTB, - }, - [28] = { - .mask = 0x00100000, - .mask_reg = QEIC_CRIMR, - .pri_code = 3, - .pri_reg = QEIC_CIPRTB, - }, - [32] = { - .mask = 0x80000000, - .mask_reg = QEIC_CIMR, - .pri_code = 0, - .pri_reg = QEIC_CIPXCC, - }, - [33] = { - .mask = 0x40000000, - .mask_reg = QEIC_CIMR, - .pri_code = 1, - .pri_reg = QEIC_CIPXCC, - }, - [34] = { - .mask = 0x20000000, - .mask_reg = QEIC_CIMR, - .pri_code = 2, - .pri_reg = QEIC_CIPXCC, - }, - [35] = { - .mask = 0x10000000, - .mask_reg = QEIC_CIMR, - .pri_code = 3, - .pri_reg = QEIC_CIPXCC, - }, - [36] = { - .mask = 0x08000000, - .mask_reg = QEIC_CIMR, - .pri_code = 4, - .pri_reg = QEIC_CIPXCC, - }, - [40] = { - .mask = 0x00800000, - .mask_reg = QEIC_CIMR, - .pri_code = 0, - .pri_reg = QEIC_CIPYCC, - }, - [41] = { - .mask = 0x00400000, - .mask_reg = QEIC_CIMR, - .pri_code = 1, - .pri_reg = QEIC_CIPYCC, - }, - [42] = { - .mask = 0x00200000, - .mask_reg = QEIC_CIMR, - .pri_code = 2, - .pri_reg = QEIC_CIPYCC, - }, - [43] = { - .mask = 0x00100000, - .mask_reg = QEIC_CIMR, - .pri_code = 3, - .pri_reg = QEIC_CIPYCC, - }, -}; - -static inline u32 qe_ic_read(volatile __be32 __iomem * base, unsigned int reg) -{ - return in_be32(base + (reg >> 2)); -} - -static inline void qe_ic_write(volatile __be32 __iomem * base, unsigned int reg, - u32 value) -{ - out_be32(base + (reg >> 2), value); -} - -static inline struct qe_ic *qe_ic_from_irq(unsigned int virq) -{ - return irq_get_chip_data(virq); -} - -static inline struct qe_ic *qe_ic_from_irq_data(struct irq_data *d) -{ - return irq_data_get_irq_chip_data(d); -} - -static void qe_ic_unmask_irq(struct irq_data *d) -{ - struct qe_ic *qe_ic = qe_ic_from_irq_data(d); - unsigned int src = irqd_to_hwirq(d); - unsigned long flags; - u32 temp; - - raw_spin_lock_irqsave(&qe_ic_lock, flags); - - temp = qe_ic_read(qe_ic->regs, qe_ic_info[src].mask_reg); - qe_ic_write(qe_ic->regs, qe_ic_info[src].mask_reg, - temp | qe_ic_info[src].mask); - - raw_spin_unlock_irqrestore(&qe_ic_lock, flags); -} - -static void qe_ic_mask_irq(struct irq_data *d) -{ - struct qe_ic *qe_ic = qe_ic_from_irq_data(d); - unsigned int src = irqd_to_hwirq(d); - unsigned long flags; - u32 temp; - - raw_spin_lock_irqsave(&qe_ic_lock, flags); - - temp = qe_ic_read(qe_ic->regs, qe_ic_info[src].mask_reg); - qe_ic_write(qe_ic->regs, qe_ic_info[src].mask_reg, - temp & ~qe_ic_info[src].mask); - - /* Flush the above write before enabling interrupts; otherwise, - * spurious interrupts will sometimes happen. To be 100% sure - * that the write has reached the device before interrupts are - * enabled, the mask register would have to be read back; however, - * this is not required for correctness, only to avoid wasting - * time on a large number of spurious interrupts. In testing, - * a sync reduced the observed spurious interrupts to zero. - */ - mb(); - - raw_spin_unlock_irqrestore(&qe_ic_lock, flags); -} - -static struct irq_chip qe_ic_irq_chip = { - .name = "QEIC", - .irq_unmask = qe_ic_unmask_irq, - .irq_mask = qe_ic_mask_irq, - .irq_mask_ack = qe_ic_mask_irq, -}; - -static int qe_ic_host_match(struct irq_domain *h, struct device_node *node, - enum irq_domain_bus_token bus_token) -{ - /* Exact match, unless qe_ic node is NULL */ - struct device_node *of_node = irq_domain_get_of_node(h); - return of_node == NULL || of_node == node; -} - -static int qe_ic_host_map(struct irq_domain *h, unsigned int virq, - irq_hw_number_t hw) -{ - struct qe_ic *qe_ic = h->host_data; - struct irq_chip *chip; - - if (hw >= ARRAY_SIZE(qe_ic_info)) { - pr_err("%s: Invalid hw irq number for QEIC\n", __func__); - return -EINVAL; - } - - if (qe_ic_info[hw].mask == 0) { - printk(KERN_ERR "Can't map reserved IRQ\n"); - return -EINVAL; - } - /* Default chip */ - chip = &qe_ic->hc_irq; - - irq_set_chip_data(virq, qe_ic); - irq_set_status_flags(virq, IRQ_LEVEL); - - irq_set_chip_and_handler(virq, chip, handle_level_irq); - - return 0; -} - -static const struct irq_domain_ops qe_ic_host_ops = { - .match = qe_ic_host_match, - .map = qe_ic_host_map, - .xlate = irq_domain_xlate_onetwocell, -}; - -/* Return an interrupt vector or NO_IRQ if no interrupt is pending. */ -unsigned int qe_ic_get_low_irq(struct qe_ic *qe_ic) -{ - int irq; - - BUG_ON(qe_ic == NULL); - - /* get the interrupt source vector. */ - irq = qe_ic_read(qe_ic->regs, QEIC_CIVEC) >> 26; - - if (irq == 0) - return NO_IRQ; - - return irq_linear_revmap(qe_ic->irqhost, irq); -} - -/* Return an interrupt vector or NO_IRQ if no interrupt is pending. */ -unsigned int qe_ic_get_high_irq(struct qe_ic *qe_ic) -{ - int irq; - - BUG_ON(qe_ic == NULL); - - /* get the interrupt source vector. */ - irq = qe_ic_read(qe_ic->regs, QEIC_CHIVEC) >> 26; - - if (irq == 0) - return NO_IRQ; - - return irq_linear_revmap(qe_ic->irqhost, irq); -} - -void __init qe_ic_init(struct device_node *node, unsigned int flags, - void (*low_handler)(struct irq_desc *desc), - void (*high_handler)(struct irq_desc *desc)) -{ - struct qe_ic *qe_ic; - struct resource res; - u32 temp = 0, ret, high_active = 0; - - ret = of_address_to_resource(node, 0, &res); - if (ret) - return; - - qe_ic = kzalloc(sizeof(*qe_ic), GFP_KERNEL); - if (qe_ic == NULL) - return; - - qe_ic->irqhost = irq_domain_add_linear(node, NR_QE_IC_INTS, - &qe_ic_host_ops, qe_ic); - if (qe_ic->irqhost == NULL) { - kfree(qe_ic); - return; - } - - qe_ic->regs = ioremap(res.start, resource_size(&res)); - - qe_ic->hc_irq = qe_ic_irq_chip; - - qe_ic->virq_high = irq_of_parse_and_map(node, 0); - qe_ic->virq_low = irq_of_parse_and_map(node, 1); - - if (qe_ic->virq_low == NO_IRQ) { - printk(KERN_ERR "Failed to map QE_IC low IRQ\n"); - kfree(qe_ic); - return; - } - - /* default priority scheme is grouped. If spread mode is */ - /* required, configure cicr accordingly. */ - if (flags & QE_IC_SPREADMODE_GRP_W) - temp |= CICR_GWCC; - if (flags & QE_IC_SPREADMODE_GRP_X) - temp |= CICR_GXCC; - if (flags & QE_IC_SPREADMODE_GRP_Y) - temp |= CICR_GYCC; - if (flags & QE_IC_SPREADMODE_GRP_Z) - temp |= CICR_GZCC; - if (flags & QE_IC_SPREADMODE_GRP_RISCA) - temp |= CICR_GRTA; - if (flags & QE_IC_SPREADMODE_GRP_RISCB) - temp |= CICR_GRTB; - - /* choose destination signal for highest priority interrupt */ - if (flags & QE_IC_HIGH_SIGNAL) { - temp |= (SIGNAL_HIGH << CICR_HPIT_SHIFT); - high_active = 1; - } - - qe_ic_write(qe_ic->regs, QEIC_CICR, temp); - - irq_set_handler_data(qe_ic->virq_low, qe_ic); - irq_set_chained_handler(qe_ic->virq_low, low_handler); - - if (qe_ic->virq_high != NO_IRQ && - qe_ic->virq_high != qe_ic->virq_low) { - irq_set_handler_data(qe_ic->virq_high, qe_ic); - irq_set_chained_handler(qe_ic->virq_high, high_handler); - } -} - -void qe_ic_set_highest_priority(unsigned int virq, int high) -{ - struct qe_ic *qe_ic = qe_ic_from_irq(virq); - unsigned int src = virq_to_hw(virq); - u32 temp = 0; - - temp = qe_ic_read(qe_ic->regs, QEIC_CICR); - - temp &= ~CICR_HP_MASK; - temp |= src << CICR_HP_SHIFT; - - temp &= ~CICR_HPIT_MASK; - temp |= (high ? SIGNAL_HIGH : SIGNAL_LOW) << CICR_HPIT_SHIFT; - - qe_ic_write(qe_ic->regs, QEIC_CICR, temp); -} - -/* Set Priority level within its group, from 1 to 8 */ -int qe_ic_set_priority(unsigned int virq, unsigned int priority) -{ - struct qe_ic *qe_ic = qe_ic_from_irq(virq); - unsigned int src = virq_to_hw(virq); - u32 temp; - - if (priority > 8 || priority == 0) - return -EINVAL; - if (WARN_ONCE(src >= ARRAY_SIZE(qe_ic_info), - "%s: Invalid hw irq number for QEIC\n", __func__)) - return -EINVAL; - if (qe_ic_info[src].pri_reg == 0) - return -EINVAL; - - temp = qe_ic_read(qe_ic->regs, qe_ic_info[src].pri_reg); - - if (priority < 4) { - temp &= ~(0x7 << (32 - priority * 3)); - temp |= qe_ic_info[src].pri_code << (32 - priority * 3); - } else { - temp &= ~(0x7 << (24 - priority * 3)); - temp |= qe_ic_info[src].pri_code << (24 - priority * 3); - } - - qe_ic_write(qe_ic->regs, qe_ic_info[src].pri_reg, temp); - - return 0; -} - -/* Set a QE priority to use high irq, only priority 1~2 can use high irq */ -int qe_ic_set_high_priority(unsigned int virq, unsigned int priority, int high) -{ - struct qe_ic *qe_ic = qe_ic_from_irq(virq); - unsigned int src = virq_to_hw(virq); - u32 temp, control_reg = QEIC_CICNR, shift = 0; - - if (priority > 2 || priority == 0) - return -EINVAL; - if (WARN_ONCE(src >= ARRAY_SIZE(qe_ic_info), - "%s: Invalid hw irq number for QEIC\n", __func__)) - return -EINVAL; - - switch (qe_ic_info[src].pri_reg) { - case QEIC_CIPZCC: - shift = CICNR_ZCC1T_SHIFT; - break; - case QEIC_CIPWCC: - shift = CICNR_WCC1T_SHIFT; - break; - case QEIC_CIPYCC: - shift = CICNR_YCC1T_SHIFT; - break; - case QEIC_CIPXCC: - shift = CICNR_XCC1T_SHIFT; - break; - case QEIC_CIPRTA: - shift = CRICR_RTA1T_SHIFT; - control_reg = QEIC_CRICR; - break; - case QEIC_CIPRTB: - shift = CRICR_RTB1T_SHIFT; - control_reg = QEIC_CRICR; - break; - default: - return -EINVAL; - } - - shift += (2 - priority) * 2; - temp = qe_ic_read(qe_ic->regs, control_reg); - temp &= ~(SIGNAL_MASK << shift); - temp |= (high ? SIGNAL_HIGH : SIGNAL_LOW) << shift; - qe_ic_write(qe_ic->regs, control_reg, temp); - - return 0; -} - -static struct bus_type qe_ic_subsys = { - .name = "qe_ic", - .dev_name = "qe_ic", -}; - -static struct device device_qe_ic = { - .id = 0, - .bus = &qe_ic_subsys, -}; - -static int __init init_qe_ic_sysfs(void) -{ - int rc; - - printk(KERN_DEBUG "Registering qe_ic with sysfs...\n"); - - rc = subsys_system_register(&qe_ic_subsys, NULL); - if (rc) { - printk(KERN_ERR "Failed registering qe_ic sys class\n"); - return -ENODEV; - } - rc = device_register(&device_qe_ic); - if (rc) { - printk(KERN_ERR "Failed registering qe_ic sys device\n"); - return -ENODEV; - } - return 0; -} - -subsys_initcall(init_qe_ic_sysfs); diff --git a/drivers/soc/fsl/qe/qe_ic.h b/drivers/soc/fsl/qe/qe_ic.h deleted file mode 100644 index 926a2ed..0000000 --- a/drivers/soc/fsl/qe/qe_ic.h +++ /dev/null @@ -1,103 +0,0 @@ -/* - * drivers/soc/fsl/qe/qe_ic.h - * - * QUICC ENGINE Interrupt Controller Header - * - * Copyright (C) 2006 Freescale Semiconductor, Inc. All rights reserved. - * - * Author: Li Yang - * Based on code from Shlomi Gridish - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ -#ifndef _POWERPC_SYSDEV_QE_IC_H -#define _POWERPC_SYSDEV_QE_IC_H - -#include - -#define NR_QE_IC_INTS 64 - -/* QE IC registers offset */ -#define QEIC_CICR 0x00 -#define QEIC_CIVEC 0x04 -#define QEIC_CRIPNR 0x08 -#define QEIC_CIPNR 0x0c -#define QEIC_CIPXCC 0x10 -#define QEIC_CIPYCC 0x14 -#define QEIC_CIPWCC 0x18 -#define QEIC_CIPZCC 0x1c -#define QEIC_CIMR 0x20 -#define QEIC_CRIMR 0x24 -#define QEIC_CICNR 0x28 -#define QEIC_CIPRTA 0x30 -#define QEIC_CIPRTB 0x34 -#define QEIC_CRICR 0x3c -#define QEIC_CHIVEC 0x60 - -/* Interrupt priority registers */ -#define CIPCC_SHIFT_PRI0 29 -#define CIPCC_SHIFT_PRI1 26 -#define CIPCC_SHIFT_PRI2 23 -#define CIPCC_SHIFT_PRI3 20 -#define CIPCC_SHIFT_PRI4 13 -#define CIPCC_SHIFT_PRI5 10 -#define CIPCC_SHIFT_PRI6 7 -#define CIPCC_SHIFT_PRI7 4 - -/* CICR priority modes */ -#define CICR_GWCC 0x00040000 -#define CICR_GXCC 0x00020000 -#define CICR_GYCC 0x00010000 -#define CICR_GZCC 0x00080000 -#define CICR_GRTA 0x00200000 -#define CICR_GRTB 0x00400000 -#define CICR_HPIT_SHIFT 8 -#define CICR_HPIT_MASK 0x00000300 -#define CICR_HP_SHIFT 24 -#define CICR_HP_MASK 0x3f000000 - -/* CICNR */ -#define CICNR_WCC1T_SHIFT 20 -#define CICNR_ZCC1T_SHIFT 28 -#define CICNR_YCC1T_SHIFT 12 -#define CICNR_XCC1T_SHIFT 4 - -/* CRICR */ -#define CRICR_RTA1T_SHIFT 20 -#define CRICR_RTB1T_SHIFT 28 - -/* Signal indicator */ -#define SIGNAL_MASK 3 -#define SIGNAL_HIGH 2 -#define SIGNAL_LOW 0 - -struct qe_ic { - /* Control registers offset */ - volatile u32 __iomem *regs; - - /* The remapper for this QEIC */ - struct irq_domain *irqhost; - - /* The "linux" controller struct */ - struct irq_chip hc_irq; - - /* VIRQ numbers of QE high/low irqs */ - unsigned int virq_high; - unsigned int virq_low; -}; - -/* - * QE interrupt controller internal structure - */ -struct qe_ic_info { - u32 mask; /* location of this source at the QIMR register. */ - u32 mask_reg; /* Mask register offset */ - u8 pri_code; /* for grouped interrupts sources - the interrupt - code as appears at the group priority register */ - u32 pri_reg; /* Group priority register offset */ -}; - -#endif /* _POWERPC_SYSDEV_QE_IC_H */