From patchwork Mon Nov 21 21:10:06 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Matthew R. 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Ochs" To: Bjorn Helgaas , linux-pci@vger.kernel.org, Ian Munsie , Frederic Barrat , linuxppc-dev@lists.ozlabs.org Subject: [PATCH 2/2] cxl: Set VPD timeout to avoid access failures Date: Mon, 21 Nov 2016 15:10:06 -0600 X-Mailer: git-send-email 2.1.0 In-Reply-To: <1479762225-51440-1-git-send-email-mrochs@linux.vnet.ibm.com> References: <1479762225-51440-1-git-send-email-mrochs@linux.vnet.ibm.com> X-TM-AS-GCONF: 00 X-Content-Scanned: Fidelis XPS MAILER x-cbid: 16112121-0004-0000-0000-000010E6C96E X-IBM-SpamModules-Scores: X-IBM-SpamModules-Versions: BY=3.00006118; HX=3.00000240; KW=3.00000007; PH=3.00000004; SC=3.00000189; SDB=6.00783573; UDB=6.00378419; IPR=6.00561193; BA=6.00004898; NDR=6.00000001; ZLA=6.00000005; ZF=6.00000009; ZB=6.00000000; ZP=6.00000000; ZH=6.00000000; ZU=6.00000002; MB=3.00013398; XFM=3.00000011; UTC=2016-11-21 21:10:13 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 16112121-0005-0000-0000-00007AC51057 Message-Id: <1479762606-51632-1-git-send-email-mrochs@linux.vnet.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2016-11-21_13:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=0 malwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1609300000 definitions=main-1611210351 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Uma Krishnan Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" Some IBM CXL devices can take up to ~120ms to complete a VPD access transaction when under heavy load. With an existing default VPD timeout of 50ms, reads/writes can fail despite there not being an issue with the underlying hardware. To avoid these false failures, increase the VPD wait timeout for certain CXL devices to a value that allows appropriate VPD access delay when faced with a worst-case scenario. Signed-off-by: Matthew R. Ochs Reviewed-by: Andrew Donnellan Acked-by: Frederic Barrat --- drivers/misc/cxl/pci.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/misc/cxl/pci.c b/drivers/misc/cxl/pci.c index e96be9c..56a67cf 100644 --- a/drivers/misc/cxl/pci.c +++ b/drivers/misc/cxl/pci.c @@ -1675,6 +1675,10 @@ bool cxl_slot_is_supported(struct pci_dev *dev, int flags) } EXPORT_SYMBOL_GPL(cxl_slot_is_supported); +static bool cxl_pci_is_slow_vpd_device(struct pci_dev *dev) +{ + return dev->device == 0x0601; +} static int cxl_probe(struct pci_dev *dev, const struct pci_device_id *id) { @@ -1692,6 +1696,9 @@ static int cxl_probe(struct pci_dev *dev, const struct pci_device_id *id) return -ENODEV; } + if (cxl_pci_is_slow_vpd_device(dev)) + pci_set_vpd_timeout(dev, msecs_to_jiffies(125)); + if (cxl_verbose) dump_cxl_config_space(dev);