From patchwork Wed Sep 28 03:25:00 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qiang Zhao X-Patchwork-Id: 675925 X-Patchwork-Delegate: scottwood@freescale.com Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3skNhZ1r5Fz9s3v for ; Wed, 28 Sep 2016 13:38:22 +1000 (AEST) Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3skNhZ12PxzDsfl for ; Wed, 28 Sep 2016 13:38:22 +1000 (AEST) X-Original-To: linuxppc-dev@lists.ozlabs.org Delivered-To: linuxppc-dev@lists.ozlabs.org Received: from NAM03-BY2-obe.outbound.protection.outlook.com (mail-by2nam03on0075.outbound.protection.outlook.com [104.47.42.75]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3skNgL4pLGzDrWw for ; Wed, 28 Sep 2016 13:37:18 +1000 (AEST) Received: from BN6PR03CA0069.namprd03.prod.outlook.com (10.173.137.31) by DM5PR03MB2444.namprd03.prod.outlook.com (10.168.233.14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P384) id 15.1.639.5; Wed, 28 Sep 2016 03:37:14 +0000 Received: from BY2FFO11FD025.protection.gbl (2a01:111:f400:7c0c::186) by BN6PR03CA0069.outlook.office365.com (2603:10b6:404:4c::31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P384) id 15.1.639.5 via Frontend Transport; Wed, 28 Sep 2016 03:37:14 +0000 Authentication-Results: spf=fail (sender IP is 192.88.158.2) smtp.mailfrom=nxp.com; nxp.com; dkim=none (message not signed) header.d=none; nxp.com; dmarc=fail action=none header.from=nxp.com; nxp.com; dkim=none (message not signed) header.d=none; Received-SPF: Fail (protection.outlook.com: domain of nxp.com does not designate 192.88.158.2 as permitted sender) receiver=protection.outlook.com; client-ip=192.88.158.2; helo=az84smr01.freescale.net; Received: from az84smr01.freescale.net (192.88.158.2) by BY2FFO11FD025.mail.protection.outlook.com (10.1.15.214) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.629.5 via Frontend Transport; Wed, 28 Sep 2016 03:37:13 +0000 Received: from titan.ap.freescale.net ([10.192.208.233]) by az84smr01.freescale.net (8.14.3/8.14.0) with ESMTP id u8S3b9BM027236; Tue, 27 Sep 2016 20:37:10 -0700 From: Zhao Qiang To: , Subject: [PATCH v6 1/4] irqchip/qeic: move qeic driver from drivers/soc/fsl/qe Date: Wed, 28 Sep 2016 11:25:00 +0800 Message-ID: <1475033103-18192-1-git-send-email-qiang.zhao@nxp.com> X-Mailer: git-send-email 2.1.0.27.g96db324 X-EOPAttributedMessage: 0 X-Matching-Connectors: 131195074340549294; (91ab9b29-cfa4-454e-5278-08d120cd25b8); () X-Forefront-Antispam-Report: CIP:192.88.158.2; IPV:NLI; CTRY:US; EFV:NLI; SFV:NSPM; SFS:(10009020)(6009001)(7916002)(2980300002)(1110001)(1109001)(339900001)(189002)(199003)(48376002)(5003940100001)(92566002)(36756003)(77096005)(104016004)(50466002)(47776003)(586003)(2906002)(68736007)(4326007)(189998001)(81166006)(50986999)(87936001)(81156014)(11100500001)(356003)(85426001)(69596002)(19580405001)(7846002)(19580395003)(33646002)(50226002)(8936002)(5660300001)(305945005)(229853001)(575784001)(105606002)(626004)(5001770100001)(97736004)(8676002)(86362001)(106466001)(8666005)(7059030)(2004002); DIR:OUT; SFP:1101; SCL:1; SRVR:DM5PR03MB2444; H:az84smr01.freescale.net; FPR:; SPF:Fail; PTR:InfoDomainNonexistent; MX:1; A:1; LANG:en; X-Microsoft-Exchange-Diagnostics: 1; BY2FFO11FD025; 1:731mkIYenOAt0dzHT4W9HF8XpqwSubDj9b3CiU8lEUZGMwWKp3QOEeIORyU2Rps1qapGnmyOSMqsPya/7jrYDl8JDlj9xa9Iu/94FlSDmhEZyH8G+1otvL83Yy23ALKbf2KBUJqfencIMdvsTgI5uvM3/tU6YMnclhC09L7KC3FX5D1qO/1lva0Xpfo/EMfftmvA+dXPEdDJJCimQfV6O2W4LDCgy/eBoqYmqtFcRLsDOJAdTj15xuel66fblkDjZPx58wmrUplHwvR6pTnSvaW7UbIyrgDKRj82nIXyBuDFTWa3FL6lAiQOygaaVAxtZz6m0f2Ld4Nj3DiMV5zQitZYPGfIEpJ2mboT2Qc5TEdyXN21NThd/OIFMnZsNaNSgPUQjqXxTQhvugbr7HUXxjO6u5NQGO5bSzq93/ljCoprDhXCd6jCW3uD6E230Zmi8wHd4b/6kpLEwH07pl8+gUM8TJ6aLYlidAT8QeNnW2qw/FajUum8hFaTbp9A1hrqk+uJfeX1eTPOyXw35gH98Y94VUNx1PZT7mJodrdWpQoGS8o5M4GgrfNauICZvUeev6c0GJvbRae3mnRfhayO0tWPFPoVPxjNXA9JD4ID2/fNyVQ8c4IrDk+UX8P0tiKT2jwVlM8cI33X4/W6k4AEPlmX5wFQJxiGLUlpzATPUJoqQ8im81kcDjrny6DK8E4W0mYYJqpos7c1o5fco+AJBwRCnnZ7ScuR+nWjd6g6pFF/nU/mHQBWF/hrhsOmCgQ3 MIME-Version: 1.0 X-MS-Office365-Filtering-Correlation-Id: c6510327-f8e4-4b16-67b6-08d3e750bcbd X-Microsoft-Exchange-Diagnostics: 1; DM5PR03MB2444; 2:kiYDJDcCo97C5rrY9yknXba+DJa5M7E0sLHCIRVNXnXe+uLxv2AHYmDalmOSb+vHPRNIm/5nRWv3x/8oXToryM9+APvfolKsJJnlVvt2vKdpSwytObepeByL0I0GdreVL6gFHwBVAWwpLNauA16ll3dd/JQAi/P3iUK+sO7aVfTbON69lc5BwvDV8kgNjk/X; 3:pvkBzZtaZIHSVkUMnQ8QpJUQjE1NQAD8U4GuMvL7PR/1sWlvDZiGXL/pp2AuAIwUfGpiSsCG1o/Xb+CyN1oilYoFEiH71sWFbUEcYe6tqB0FLbRBK88JRkGCjEHVHjR7p+BVoQxH8nLyciYRsL98GrmDz1TWGsRNul5at1GwKiNae1y9WqZHIbWFn1ABh8FXMChX3/vl9g3Q66ovhhYrkM+KH4vH8uXpcJfKrmGkE7M= X-Microsoft-Antispam: UriScan:;BCL:0;PCL:0;RULEID:;SRVR:DM5PR03MB2444; X-Microsoft-Exchange-Diagnostics: 1; DM5PR03MB2444; 25:xdgJB0NkqSWsaObco96PAJo3D4I/fI5QKYB+v4+1Pv5MQdRXgWcGgNRpKTA6qFxUgpXL3DFbVI6sRDYbZ9i/x6pj2hRgV7iVeufa2jtAWNou7UgiETlNRo6yO3v4mM06TSuhrKWBvQ0TzoZHSd3vY9orVFfQL5JeLckOy+VX5oSgSPdx2RT1Vinn8/FD8wbKivQvWDnM/94c+z8f+qS8DRF0TEJ9RgjqkceM+rjkD2Q8cxRiYtu4fKM5aZY/u4GaYBLMSZknylBlYGB7RTIdbmWRnYYYAmgaSykQAtHaRlzMx4nDT6O4QAxeFv0swNS2ETU/EozXTCTf/C4jqW/Tonw13ZqOI0XU9JdTOeO3siL0vKevKVHVQujvbAlxoRJLxvluNqdBR5U7YZHZsy2n8hfk+qH1Qi8vGNB06jGI9n5omBRhoNdY+f1FKgh1mn3rqJybIJNoFfBkYuhxvTtNsSUgMjO80XRMu0YHwo4FGwIS5rXYbm/ANd326H0j/4MLx1N4doGaDrLfeGC+A+Gowy/k304GTlpsIG1BWnU19wgTSAVqJ4astbqsAaFaX+Mbc9UlptHFNDjTEv0W6Z3O2AxZRdRkp5ZHoABv+iQWHEfAlACH8qh2wBEMNavZDBwbYBN+AkN2jY/qOKU1cprJ5d/KgRZQNkwIkzb9ZpPYrFq/qnklBP8USgdSlPGpkUnwRWrcSErNI6KnGZLZ/ptHmkjJngM9Xhid9tVZddhv1vc= X-Microsoft-Exchange-Diagnostics: 1; DM5PR03MB2444; 31:+FGVYv2BveY+MCslAl5W0bNinMlp82V3M9oPCJCA2gHVkF3p18jXK/gBZz96nTxAr4/f/10BgRDyIicv/W7DHWSEP1nlQFuzayLMToXhhhCxgqJfG87NMarLNri/8Z3MVUyrUM6y5SAX/8DN/OhMqjVT2qWAiBe5E43PBgAiR+nETjLbdG8EWqj3QqymUYt9F/K7o7n01oM77TJiGRNuHJak3JjJ+Y3FPyOEYMEOhBE=; 4:5/xGHJfYBAYlhkE0lNfhKwCWAWEsS10M7UkN6mNS16ixydP8+EZUc5dYsaPH6p9eYFSMVxkFn71BqIvZ6Oanb5DUkH8MjEmCqpvDVRdCT+WkJjQHBGyucM/sArTi5T93DVSm/iJdPo/5pwKFLxfH0Ol6uicaso6vaweGVJsgNKPqPoRU407wDlBbqn63Togj56ffZ3JORu1Bz4rtjMTLbktoDgvgL3qwkgUW/fuK7+zsP+o23gB6PmwNMYAeG0cq7l1XJ8+9qoV5EfBtxWF5acMmu365z9fx5spWFI2HkG34hxzfXFjIbsTqo47p/r6c9JLbhIqKYNhja1nkZxprwW4xbqrfwyuGjzBEBuY+s0fdI/2hRdCV/z7xuLnVg118jSdc1op84kir8Y++n6YAIUiTeEvm82WqJ1d4AWgZaHvrzZ74s9g08U/bbVGAE37Di8+mkjEBJ22ihz1Rv/Y7bYL3VLW1iZj/wNB7QSgYEC9LEcS8ezt7wGcNF5mWhBE18Ucbf37eCBE486HtcKaSuabqhN+Gdra+TaA8VXxrcSHPA6q7TXDWWVZlPjEv/S80Y0qXGJqTwaigkj6Py4fsHw== X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:(185117386973197)(101931422205132); X-Exchange-Antispam-Report-CFA-Test: BCL:0; PCL:0; RULEID:(6040176)(601004)(2401047)(5005006)(8121501046)(13017025)(13015025)(13024025)(13018025)(13023025)(10201501046)(3002001)(6055026); SRVR:DM5PR03MB2444; BCL:0; PCL:0; RULEID:(400006); SRVR:DM5PR03MB2444; X-Forefront-PRVS: 0079056367 X-Microsoft-Exchange-Diagnostics: =?us-ascii?Q?1; DM5PR03MB2444; 23:AHrxeRmPrqW3+6ckEKX3QvFAzqHoN0n63g+brnDuk?= =?us-ascii?Q?d6AkTBjEPpeFIYj0TiRSirlYt1xljEQIQ7nBZrU46wa81kJ36NL9FeWFTn+4?= =?us-ascii?Q?LYtoHeMM7uwo1aAWmogNuN8DbLZegYDQCh+x5yQLqxuRQ69qkaQGbLIy12pQ?= =?us-ascii?Q?+nHkgMwLLcOCHBQE7JM6pPYgyaNkvfkoBC1xtZo8dA62o5RnojDAEoOOvNNN?= =?us-ascii?Q?SmPohaOZ1B0x9ec7lEtqISB3wZJ3E3UvxiV/W90gHOZMPjvBJjEmS3TLaZV+?= =?us-ascii?Q?O3psbwfX3hjK8B6jOx55AK7/e2vUgtQlcwMBGMMep85qJk+/9+h5yvtQY36x?= =?us-ascii?Q?DLEA1hcMBh6rULf1ZzHAhrdfeDWft4tvXeV5EMHVLVci6PlEw5PiBmyiEMsK?= =?us-ascii?Q?CCrw9gH2q9FEBRaJM0JBpbEQLIvKFQPRVupN7e9+F3eV4YkarRr/Y3Bumbbb?= =?us-ascii?Q?dQnoduYVh0/pKvq1b4FoheZSgx9lycVjkyRJu6XeTcAWKhdl1od90nbDtxHL?= =?us-ascii?Q?c0VGT/5IogaMyixSWjbCrmQbB03QEGHwI1f3/X7gDqguNrEpZO9GDBqhguHH?= =?us-ascii?Q?uOGhjAHvKYjMWGRiR11h+hYqQaWUSWIpesYO5TPKwbLrzWUoEUJsOxcEn9lN?= =?us-ascii?Q?sUNFBxn9X2RnENoSDSNr9wwQc6jrRfFsVu2bBEvyMslSdGqpw6kPIH7Sr15R?= =?us-ascii?Q?+blF9PkSQIaEj3ui/4CfhozQ6JJMrk62FpDEvyUZZT/+YarxPx5l0QJmmENT?= =?us-ascii?Q?u9K/bTAUMVMD88jXrjlMszBSAU17uQWya8r8JkcaLzgFfj63uSFuDJoOjO/U?= =?us-ascii?Q?fo2fS51xp4FmnDSAMyDTHagcGKbSu4y56zjIhM4NvT2YWErTSWRdQrM3JuF8?= =?us-ascii?Q?rtniAo92eyAX1OEfO97ApbCYw9hk6IJU4mj9ZHNfsyXVxb/OLHXp2qBnZPlK?= =?us-ascii?Q?2IBXz03lzkcg+TMT5l1SjGCwUecwNP1rd44XSpTDPyCBa8s+FusRGdK8+C9x?= =?us-ascii?Q?tmzhpJa0j726UU/HaBi5zf0zEQ1pxk9s3oeKc+5O43De6jzOEr6uiXMSxzqa?= =?us-ascii?Q?4CdXLvvqafAAzzFUODUz+hEMTZXOSX4VD8yL6c9+zuqfm0xZrgJd81R/mwbF?= =?us-ascii?Q?6lF9vvcPnm3DJ9lv5SooIViblm7w7ym5PiwMCF01M3X2tcEg8yKT3oL3NYuW?= =?us-ascii?Q?JtMksHvjv1hlHo=3D?= X-Microsoft-Exchange-Diagnostics: 1; DM5PR03MB2444; 6:K8bHdHsSxIAl+lv7QVjZu/0sxMZNWocjkUM+m73zzicHa7efGQk3zd68AwWiY0vmFSzeQ8ZTWqgc0WxCInImIs467Ont6IY0Fgf/CJx0SFpD3+RCBBlHxzIyzgO1g4uCUauJafP0Svj762T5u2/uKKw3buTfjCW6CWzfvrNlNRYBJtGTVoe9OaXwh9sNcwq6sdKfTGOswhH+p88eo583PMnD2iInp1sY5LjxzGKXi2xLtjDD4LikhoOSH0weBGnu0UBTqsOVnUwdMFhOZyUd9FAmbXpJfIVg1mv20MDEgig=; 5:4I9KhywQFVl5EHBUh490R+tE42bqddzlIkKRQUG0C4kfbjrS+SfDWVz2N6N2gIC1SE3ieKPo9vdMM4oT2T5T4DxtmJqGZhvPDg/DTPkMaV7dFYlzEwsG1XctuPGzagieNy/o6QFPBtzycq3gizbVr8tXRoZ2oXDvKdCWD6arIwE=; 24:5wt/kQKagScX/uSgSEusOoGEh83P9FS/CW3h9Wkn1lQYHbTevvyBA7/a5DOVBjrUdDW/vv85TlvqI/u+l6BrMPyhfuSPfVkJ2datsaE8Uog=; 7:2/Xbwbw1Mo4X3Ol5INFrTJj56yYOO41nM0gbTmFg/mJPiKL98nWdbYtBnc130aKFdU0NoeDe2OwzXLzJz0Rbr6I90yDW+grCIod8Fm8HEZuPwmFyi6YIcbVdidROBH3mPbMt9tRHuyvQdYWeUycIt9MmBk3u+gDZ1P0/rBJ2mM49Z7oCkp/k8CDj83hv7HhrsYDDqhduTiHT7y1ES/zF+i/+FTM0c6sJ95CuG9DeFk5Tov51fjDMTv98qidO7LCwRgZweExCXcn9lHeALWwjlf4C+64s2O2Kq+BYotUn07vtBT9zvjNm4ICPj3iA6nY8 SpamDiagnosticOutput: 1:99 SpamDiagnosticMetadata: NSPM X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Sep 2016 03:37:13.8209 (UTC) X-MS-Exchange-CrossTenant-Id: 5afe0b00-7697-4969-b663-5eab37d5f47e X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=5afe0b00-7697-4969-b663-5eab37d5f47e; Ip=[192.88.158.2]; Helo=[az84smr01.freescale.net] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR03MB2444 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jason@lakedaemon.net, marc.zyngier@arm.com, linux-kernel@vger.kernel.org, xiaobo.xie@nxp.com, linuxppc-dev@lists.ozlabs.org, Zhao Qiang Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" move the driver from drivers/soc/fsl/qe to drivers/irqchip, merge qe_ic.h and qe_ic.c into irq-qeic.c. Signed-off-by: Zhao Qiang --- Changes for v2: - modify the subject and commit msg Changes for v3: - merge .h file to .c, rename it with irq-qeic.c Changes for v4: - modify comments Changes for v5: - disable rename detection Changes for v6: - rebase drivers/irqchip/Makefile | 1 + drivers/{soc/fsl/qe/qe_ic.c => irqchip/irq-qeic.c} | 95 ++++++++++++++++++- drivers/soc/fsl/qe/Makefile | 2 +- drivers/soc/fsl/qe/qe_ic.h | 103 --------------------- 4 files changed, 94 insertions(+), 107 deletions(-) rename drivers/{soc/fsl/qe/qe_ic.c => irqchip/irq-qeic.c} (85%) delete mode 100644 drivers/soc/fsl/qe/qe_ic.h diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile index 4c203b6..face608 100644 --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile @@ -71,3 +71,4 @@ obj-$(CONFIG_MVEBU_ODMI) += irq-mvebu-odmi.o obj-$(CONFIG_LS_SCFG_MSI) += irq-ls-scfg-msi.o obj-$(CONFIG_EZNPS_GIC) += irq-eznps.o obj-$(CONFIG_ARCH_ASPEED) += irq-aspeed-vic.o +obj-$(CONFIG_QUICC_ENGINE) += irq-qeic.o diff --git a/drivers/soc/fsl/qe/qe_ic.c b/drivers/irqchip/irq-qeic.c similarity index 85% rename from drivers/soc/fsl/qe/qe_ic.c rename to drivers/irqchip/irq-qeic.c index ec2ca86..48ceded 100644 --- a/drivers/soc/fsl/qe/qe_ic.c +++ b/drivers/irqchip/irq-qeic.c @@ -1,7 +1,7 @@ /* - * arch/powerpc/sysdev/qe_lib/qe_ic.c + * drivers/irqchip/irq-qeic.c * - * Copyright (C) 2006 Freescale Semiconductor, Inc. All rights reserved. + * Copyright (C) 2016 Freescale Semiconductor, Inc. All rights reserved. * * Author: Li Yang * Based on code from Shlomi Gridish @@ -30,7 +30,96 @@ #include #include -#include "qe_ic.h" +#define NR_QE_IC_INTS 64 + +/* QE IC registers offset */ +#define QEIC_CICR 0x00 +#define QEIC_CIVEC 0x04 +#define QEIC_CRIPNR 0x08 +#define QEIC_CIPNR 0x0c +#define QEIC_CIPXCC 0x10 +#define QEIC_CIPYCC 0x14 +#define QEIC_CIPWCC 0x18 +#define QEIC_CIPZCC 0x1c +#define QEIC_CIMR 0x20 +#define QEIC_CRIMR 0x24 +#define QEIC_CICNR 0x28 +#define QEIC_CIPRTA 0x30 +#define QEIC_CIPRTB 0x34 +#define QEIC_CRICR 0x3c +#define QEIC_CHIVEC 0x60 + +/* Interrupt priority registers */ +#define CIPCC_SHIFT_PRI0 29 +#define CIPCC_SHIFT_PRI1 26 +#define CIPCC_SHIFT_PRI2 23 +#define CIPCC_SHIFT_PRI3 20 +#define CIPCC_SHIFT_PRI4 13 +#define CIPCC_SHIFT_PRI5 10 +#define CIPCC_SHIFT_PRI6 7 +#define CIPCC_SHIFT_PRI7 4 + +/* CICR priority modes */ +#define CICR_GWCC 0x00040000 +#define CICR_GXCC 0x00020000 +#define CICR_GYCC 0x00010000 +#define CICR_GZCC 0x00080000 +#define CICR_GRTA 0x00200000 +#define CICR_GRTB 0x00400000 +#define CICR_HPIT_SHIFT 8 +#define CICR_HPIT_MASK 0x00000300 +#define CICR_HP_SHIFT 24 +#define CICR_HP_MASK 0x3f000000 + +/* CICNR */ +#define CICNR_WCC1T_SHIFT 20 +#define CICNR_ZCC1T_SHIFT 28 +#define CICNR_YCC1T_SHIFT 12 +#define CICNR_XCC1T_SHIFT 4 + +/* CRICR */ +#define CRICR_RTA1T_SHIFT 20 +#define CRICR_RTB1T_SHIFT 28 + +/* Signal indicator */ +#define SIGNAL_MASK 3 +#define SIGNAL_HIGH 2 +#define SIGNAL_LOW 0 + +struct qe_ic { + /* Control registers offset */ + volatile u32 __iomem *regs; + + /* The remapper for this QEIC */ + struct irq_domain *irqhost; + + /* The "linux" controller struct */ + struct irq_chip hc_irq; + + /* VIRQ numbers of QE high/low irqs */ + unsigned int virq_high; + unsigned int virq_low; +}; + +/* + * QE interrupt controller internal structure + */ +struct qe_ic_info { + /* location of this source at the QIMR register. */ + u32 mask; + + /* Mask register offset */ + u32 mask_reg; + + /* + * for grouped interrupts sources - the interrupt + * code as appears at the group priority register + */ + u8 pri_code; + + /* Group priority register offset */ + u32 pri_reg; +}; static DEFINE_RAW_SPINLOCK(qe_ic_lock); diff --git a/drivers/soc/fsl/qe/Makefile b/drivers/soc/fsl/qe/Makefile index 2031d38..51e4726 100644 --- a/drivers/soc/fsl/qe/Makefile +++ b/drivers/soc/fsl/qe/Makefile @@ -1,7 +1,7 @@ # # Makefile for the linux ppc-specific parts of QE # -obj-$(CONFIG_QUICC_ENGINE)+= qe.o qe_common.o qe_ic.o qe_io.o +obj-$(CONFIG_QUICC_ENGINE)+= qe.o qe_common.o qe_io.o obj-$(CONFIG_CPM) += qe_common.o obj-$(CONFIG_UCC) += ucc.o obj-$(CONFIG_UCC_SLOW) += ucc_slow.o diff --git a/drivers/soc/fsl/qe/qe_ic.h b/drivers/soc/fsl/qe/qe_ic.h deleted file mode 100644 index 926a2ed..0000000 --- a/drivers/soc/fsl/qe/qe_ic.h +++ /dev/null @@ -1,103 +0,0 @@ -/* - * drivers/soc/fsl/qe/qe_ic.h - * - * QUICC ENGINE Interrupt Controller Header - * - * Copyright (C) 2006 Freescale Semiconductor, Inc. All rights reserved. - * - * Author: Li Yang - * Based on code from Shlomi Gridish - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ -#ifndef _POWERPC_SYSDEV_QE_IC_H -#define _POWERPC_SYSDEV_QE_IC_H - -#include - -#define NR_QE_IC_INTS 64 - -/* QE IC registers offset */ -#define QEIC_CICR 0x00 -#define QEIC_CIVEC 0x04 -#define QEIC_CRIPNR 0x08 -#define QEIC_CIPNR 0x0c -#define QEIC_CIPXCC 0x10 -#define QEIC_CIPYCC 0x14 -#define QEIC_CIPWCC 0x18 -#define QEIC_CIPZCC 0x1c -#define QEIC_CIMR 0x20 -#define QEIC_CRIMR 0x24 -#define QEIC_CICNR 0x28 -#define QEIC_CIPRTA 0x30 -#define QEIC_CIPRTB 0x34 -#define QEIC_CRICR 0x3c -#define QEIC_CHIVEC 0x60 - -/* Interrupt priority registers */ -#define CIPCC_SHIFT_PRI0 29 -#define CIPCC_SHIFT_PRI1 26 -#define CIPCC_SHIFT_PRI2 23 -#define CIPCC_SHIFT_PRI3 20 -#define CIPCC_SHIFT_PRI4 13 -#define CIPCC_SHIFT_PRI5 10 -#define CIPCC_SHIFT_PRI6 7 -#define CIPCC_SHIFT_PRI7 4 - -/* CICR priority modes */ -#define CICR_GWCC 0x00040000 -#define CICR_GXCC 0x00020000 -#define CICR_GYCC 0x00010000 -#define CICR_GZCC 0x00080000 -#define CICR_GRTA 0x00200000 -#define CICR_GRTB 0x00400000 -#define CICR_HPIT_SHIFT 8 -#define CICR_HPIT_MASK 0x00000300 -#define CICR_HP_SHIFT 24 -#define CICR_HP_MASK 0x3f000000 - -/* CICNR */ -#define CICNR_WCC1T_SHIFT 20 -#define CICNR_ZCC1T_SHIFT 28 -#define CICNR_YCC1T_SHIFT 12 -#define CICNR_XCC1T_SHIFT 4 - -/* CRICR */ -#define CRICR_RTA1T_SHIFT 20 -#define CRICR_RTB1T_SHIFT 28 - -/* Signal indicator */ -#define SIGNAL_MASK 3 -#define SIGNAL_HIGH 2 -#define SIGNAL_LOW 0 - -struct qe_ic { - /* Control registers offset */ - volatile u32 __iomem *regs; - - /* The remapper for this QEIC */ - struct irq_domain *irqhost; - - /* The "linux" controller struct */ - struct irq_chip hc_irq; - - /* VIRQ numbers of QE high/low irqs */ - unsigned int virq_high; - unsigned int virq_low; -}; - -/* - * QE interrupt controller internal structure - */ -struct qe_ic_info { - u32 mask; /* location of this source at the QIMR register. */ - u32 mask_reg; /* Mask register offset */ - u8 pri_code; /* for grouped interrupts sources - the interrupt - code as appears at the group priority register */ - u32 pri_reg; /* Group priority register offset */ -}; - -#endif /* _POWERPC_SYSDEV_QE_IC_H */