From patchwork Thu Jul 21 06:44:13 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 651019 Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3rw4yn1h6Fz9sRZ for ; Thu, 21 Jul 2016 17:24:01 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b=G/kk0wR/; dkim-atps=neutral Received: from ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3rw4yn0bzPzDrHf for ; Thu, 21 Jul 2016 17:24:01 +1000 (AEST) Authentication-Results: lists.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b=G/kk0wR/; dkim-atps=neutral X-Original-To: linuxppc-dev@lists.ozlabs.org Delivered-To: linuxppc-dev@lists.ozlabs.org Received: from mail-pf0-x242.google.com (mail-pf0-x242.google.com [IPv6:2607:f8b0:400e:c00::242]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3rw46G36PKzDqTF for ; Thu, 21 Jul 2016 16:45:26 +1000 (AEST) Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b=G/kk0wR/; dkim-atps=neutral Received: by mail-pf0-x242.google.com with SMTP id i6so4904632pfe.0 for ; Wed, 20 Jul 2016 23:45:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=6MAz4sYvEIAETQk6yQa6zxR8VUrrkcC5qZzfPepFQ6I=; b=G/kk0wR/VltMmSd3vnA/hjhnya03lR6mDvdmhoouxvey2WdVW5rzfWiXaUM32NGF+R U1bwe/cH//PDZbb268mtYlLLJqwcu9WrFv/+WUpqIhw7y4z128KFwbqIj8PY7GnwRJfG Cl17FNVOS9m6UmhsQoMk9AelNokeHcKpURfs36Lfmsmi1i6TkcPAcNhQwOsWvmkb/RqO 44saem/epQW6NPozn8mKwV2Py7pLu+rzIAv6xv9iZh5wx99qQNGvf/CZkgLUcYLYkVIW gXEQ3u+fslNvnRaBF8q8eMohj/IoV/ZT6BuAAEDfTMozUlmouqy3KfqkIbufstUCkyWK 9ayw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=6MAz4sYvEIAETQk6yQa6zxR8VUrrkcC5qZzfPepFQ6I=; b=g7Lue/HKFj/nr1mKlfiOZS0/OKT7oyyJvmaiEQLQEBpDJAoJ8qoETHgtCZvn+/5oEl /UWxTIju1EkaCeBNzyOZ+4t3kwKFVo7EJPQPtTJ6d4ElBC1GGwwft96TkF06LkMXryQS fENVUMHmH4zm0PxH9K9h3YL3B4EWnuh6qN00f2T7gB/TiNN+l1VIl2eNKy7KM+syQAIz EgPDvBkvVMiUve+b+9qXxt+U12bdFpBxKA53QGE/q02RS3Krt52RIHrNDiweNf5rL+Ih 26i1tQ+JnBnyIlsJ+WUwl3uzknWJN8d4/XoZThCWTvQ4BZcsoXDNi4nCX9+T0hRZXKCi 1PqA== X-Gm-Message-State: ALyK8tIqMM69xPIm8X9a9VHz3WRgR+vBa/mgvBgbSCNzs41U1CChcejdvAFSQ1sP4I2HRw== X-Received: by 10.98.89.23 with SMTP id n23mr70955389pfb.34.1469083524858; Wed, 20 Jul 2016 23:45:24 -0700 (PDT) Received: from roar.ozlabs.ibm.com ([122.99.82.10]) by smtp.gmail.com with ESMTPSA id z10sm9071053pff.95.2016.07.20.23.45.22 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 20 Jul 2016 23:45:24 -0700 (PDT) From: Nicholas Piggin X-Google-Original-From: Nicholas Piggin To: linuxppc-dev@lists.ozlabs.org Subject: [PATCH 14/14] powerpc/pseries: exceptions use short handler load again Date: Thu, 21 Jul 2016 16:44:13 +1000 Message-Id: <1469083453-9279-15-git-send-email-npiggin@gmail.com> X-Mailer: git-send-email 2.8.1 In-Reply-To: <1469083453-9279-1-git-send-email-npiggin@gmail.com> References: <1469083453-9279-1-git-send-email-npiggin@gmail.com> X-Mailman-Approved-At: Thu, 21 Jul 2016 16:57:32 +1000 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Nicholas Piggin MIME-Version: 1.0 Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" addis generated by LOAD_HANDLER_4GB is always 0, so it is safe to use 64K handlers. Move decrementer exception back inline. Signed-off-by: Nick Piggin --- arch/powerpc/include/asm/exception-64s.h | 4 ++-- arch/powerpc/kernel/exceptions-64s.S | 21 ++++++++++++--------- 2 files changed, 14 insertions(+), 11 deletions(-) diff --git a/arch/powerpc/include/asm/exception-64s.h b/arch/powerpc/include/asm/exception-64s.h index 06e2247..eaad38f 100644 --- a/arch/powerpc/include/asm/exception-64s.h +++ b/arch/powerpc/include/asm/exception-64s.h @@ -55,7 +55,7 @@ #define __EXCEPTION_RELON_PROLOG_PSERIES_1(label, h) \ ld r12,PACAKBASE(r13); /* get high part of &label */ \ mfspr r11,SPRN_##h##SRR0; /* save SRR0 */ \ - LOAD_HANDLER_4G(r12,label); \ + LOAD_HANDLER_64K(r12,label); \ mtctr r12; \ mfspr r12,SPRN_##h##SRR1; /* and SRR1 */ \ li r10,MSR_RI; \ @@ -186,7 +186,7 @@ END_FTR_SECTION_NESTED(ftr,ftr,943) ld r12,PACAKBASE(r13); /* get high part of &label */ \ ld r10,PACAKMSR(r13); /* get MSR value for kernel */ \ mfspr r11,SPRN_##h##SRR0; /* save SRR0 */ \ - LOAD_HANDLER_4G(r12,label); \ + LOAD_HANDLER_64K(r12,label); \ mtspr SPRN_##h##SRR0,r12; \ mfspr r12,SPRN_##h##SRR1; /* and SRR1 */ \ mtspr SPRN_##h##SRR1,r10; \ diff --git a/arch/powerpc/kernel/exceptions-64s.S b/arch/powerpc/kernel/exceptions-64s.S index c317faf..462bf67 100644 --- a/arch/powerpc/kernel/exceptions-64s.S +++ b/arch/powerpc/kernel/exceptions-64s.S @@ -262,7 +262,7 @@ BEGIN_FTR_SECTION ori r11,r11,MSR_ME /* turn on ME bit */ ori r11,r11,MSR_RI /* turn on RI bit */ ld r12,PACAKBASE(r13) /* get high part of &label */ - LOAD_HANDLER_4G(r12, machine_check_handle_early) + LOAD_HANDLER_64K(r12, machine_check_handle_early) 1: mtspr SPRN_SRR0,r12 mtspr SPRN_SRR1,r11 rfid @@ -275,7 +275,7 @@ BEGIN_FTR_SECTION addi r1,r1,INT_FRAME_SIZE /* go back to previous stack frame */ ld r11,PACAKMSR(r13) ld r12,PACAKBASE(r13) - LOAD_HANDLER_4G(r12, unrecover_mce) + LOAD_HANDLER_64K(r12, unrecover_mce) li r10,MSR_ME andc r11,r11,r10 /* Turn off MSR_ME */ b 1b @@ -416,7 +416,7 @@ COMMON_HANDLER_BEGIN(machine_check_handle_early) bne 2f 1: mfspr r11,SPRN_SRR0 ld r10,PACAKBASE(r13) - LOAD_HANDLER_4G(r10,unrecover_mce) + LOAD_HANDLER_64K(r10,unrecover_mce) mtspr SPRN_SRR0,r10 ld r10,PACAKMSR(r13) /* @@ -510,7 +510,7 @@ COMMON_HANDLER_END(data_access_common) mfspr r12,SPRN_SRR1; \ mfctr r11; \ ld r10,PACAKBASE(r13); \ - LOAD_HANDLER_4G(r10, slb_miss_realmode); \ + LOAD_HANDLER_64K(r10, slb_miss_realmode); \ mtctr r10; \ bctr; #else @@ -577,7 +577,7 @@ END_MMU_FTR_SECTION_IFSET(MMU_FTR_RADIX) 2: mfspr r11,SPRN_SRR0 ld r10,PACAKBASE(r13) - LOAD_HANDLER_4G(r10,unrecov_slb) + LOAD_HANDLER_64K(r10,unrecov_slb) mtspr SPRN_SRR0,r10 ld r10,PACAKMSR(r13) mtspr SPRN_SRR1,r10 @@ -729,7 +729,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_TM) COMMON_HANDLER_END(fp_unavailable_common) -VECTOR_HANDLER_REAL_OOL_MASKABLE(decrementer, 0x900, 0x980) +VECTOR_HANDLER_REAL_MASKABLE(decrementer, 0x900, 0x980) VECTOR_HANDLER_VIRT_MASKABLE(decrementer, 0x4900, 0x4980, 0x900) TRAMP_KVM(PACA_EXGEN, 0x900) COMMON_HANDLER_ASYNC(decrementer_common, 0x900, timer_interrupt) @@ -771,7 +771,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_REAL_LE) \ #define SYSCALL_PSERIES_2_RFID \ mfspr r12,SPRN_SRR1 ; \ ld r10,PACAKBASE(r13) ; \ - LOAD_HANDLER_4G(r10, system_call_common) ; \ + LOAD_HANDLER_64K(r10, system_call_common) ; \ mtspr SPRN_SRR0,r10 ; \ ld r10,PACAKMSR(r13) ; \ mtspr SPRN_SRR1,r10 ; \ @@ -794,7 +794,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_REAL_LE) \ #define SYSCALL_PSERIES_2_DIRECT \ mflr r10 ; \ ld r12,PACAKBASE(r13) ; \ - LOAD_HANDLER_4G(r12, system_call_common) ; \ + LOAD_HANDLER_64K(r12, system_call_common) ; \ mtctr r12 ; \ mfspr r12,SPRN_SRR1 ; \ /* Re-use of r13... No spare regs to do this */ \ @@ -1317,7 +1317,10 @@ USE_FIXED_SECTION(virt_trampolines) * handlers, so that they are copied to real address 0x100 when running * a relocatable kernel. This ensures they can be reached from the short * trampoline handlers (like 0x4f00, 0x4f20, etc.) which branch - * directly, without using LOAD_HANDLER_4G(). + * directly, without using LOAD_HANDLER_*(). + * + * This needs to be aligned according to copy_and_flush, which copies + * cacheline at a time. */ .align 7 .globl __end_interrupts