From patchwork Thu Aug 13 11:51:37 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kevin Hao X-Patchwork-Id: 506981 X-Patchwork-Delegate: scottwood@freescale.com Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 53AD914027F for ; Thu, 13 Aug 2015 21:56:22 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b=xLXNCItA; dkim-atps=neutral Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 2A7C91A1D93 for ; Thu, 13 Aug 2015 21:56:22 +1000 (AEST) Authentication-Results: lists.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b=xLXNCItA; dkim-atps=neutral X-Original-To: linuxppc-dev@lists.ozlabs.org Delivered-To: linuxppc-dev@lists.ozlabs.org Received: from mail-yk0-x22a.google.com (mail-yk0-x22a.google.com [IPv6:2607:f8b0:4002:c07::22a]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id E8E9E1A1D67 for ; Thu, 13 Aug 2015 21:51:55 +1000 (AEST) Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b=xLXNCItA; dkim-atps=neutral Received: by ykay144 with SMTP id y144so38543303yka.3 for ; Thu, 13 Aug 2015 04:51:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=9nZVdwCBzSa7z4ADUqF5Fw+ZAx4qBzeTV85DpoqzIdc=; b=xLXNCItAwO/BsgSa5C01UKh3yodF2q6ljX+k3VWq9PqiW4/7n6UQ8ZspV4qZV7If4I F78UMXX+yBaL1lLxzGrdR6WN/sp0FxwlKgMAfqLtbN2gSq+x9js24L9uLTKw05LQeRFV R8lgFGAC2sYiZ4hx45sKg9jXcIXtauX8hxwNA5x0dhL9RhFlsMcB/6yYqPsDAqU14G1u PKdZNFiNUmxPyQQJwdLa1/UFlM0Fixj8hsS679VuYJh3Px/jNRS1ADh2yZtMi7PRTj6z BkhqL5YORk/OvksyPSaqf9RgdVZJOAYV+lzr/2uFI/+nUQq9mORkqQAp4ZVkKWYH2xt7 B0CA== X-Received: by 10.129.87.204 with SMTP id l195mr38454222ywb.23.1439466714038; Thu, 13 Aug 2015 04:51:54 -0700 (PDT) Received: from pek-khao-d1.corp.ad.wrs.com (unknown-178-22.windriver.com. [147.11.178.22]) by smtp.gmail.com with ESMTPSA id z193sm1815932ywd.24.2015.08.13.04.51.51 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 13 Aug 2015 04:51:53 -0700 (PDT) From: Kevin Hao To: Scott Wood Subject: [PATCH 3/3] powerpc/e6500: hw tablewalk: order the memory access when acquire/release tcd lock Date: Thu, 13 Aug 2015 19:51:37 +0800 Message-Id: <1439466697-18989-3-git-send-email-haokexin@gmail.com> X-Mailer: git-send-email 2.1.0 In-Reply-To: <1439466697-18989-1-git-send-email-haokexin@gmail.com> References: <1439466697-18989-1-git-send-email-haokexin@gmail.com> X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linuxppc-dev@lists.ozlabs.org MIME-Version: 1.0 Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" I didn't find anything unusual. But I think we do need to order the load/store of esel_next when acquire/release tcd lock. For acquire, add a data dependency to order the loads of lock and esel_next. For release, even there already have a "isync" here, but it doesn't guarantee any memory access order. So we still need "lwsync" for the two stores for lock and esel_next. Signed-off-by: Kevin Hao --- arch/powerpc/mm/tlb_low_64e.S | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/powerpc/mm/tlb_low_64e.S b/arch/powerpc/mm/tlb_low_64e.S index e4185581c5a7..964754911987 100644 --- a/arch/powerpc/mm/tlb_low_64e.S +++ b/arch/powerpc/mm/tlb_low_64e.S @@ -334,6 +334,8 @@ BEGIN_FTR_SECTION /* CPU_FTR_SMT */ * with tlbilx before overwriting. */ + andi r15,r15,0 /* add a data dependency to order the loards */ + add r11,r11,r15 /* between the lock and esel_next */ lbz r15,TCD_ESEL_NEXT(r11) rlwinm r10,r15,16,0xff0000 oris r10,r10,MAS0_TLBSEL(1)@h @@ -447,6 +449,7 @@ BEGIN_FTR_SECTION beq cr1,1f /* no unlock if lock was recursively grabbed */ li r15,0 isync + lwsync stb r15,0(r11) 1: END_FTR_SECTION_IFSET(CPU_FTR_SMT)