| Message ID | 1437544251-19016-3-git-send-email-sam.mj@au1.ibm.com (mailing list archive) |
|---|---|
| State | Accepted |
| Headers | show |
On Wed, 2015-22-07 at 05:50:51 UTC, Samuel Mendoza-Jonas wrote: > On powernv secondary cpus are returned to OPAL, and will then enter > the target kernel in big-endian. However if it is set the HILE bit > will persist, causing the first exception in the target kernel to be > delivered in litte-endian regardless of the current endianess. > > If running on top of OPAL make sure the HILE bit is reset once we've > finished waiting for all of the secondaries to be returned to OPAL. > > Signed-off-by: Samuel Mendoza-Jonas <sam.mj@au1.ibm.com> Applied to powerpc next, thanks. https://git.kernel.org/powerpc/c/e72bb8a5a884d0222311 cheers
diff --git a/arch/powerpc/platforms/powernv/setup.c b/arch/powerpc/platforms/powernv/setup.c index 53737e0..59076db 100644 --- a/arch/powerpc/platforms/powernv/setup.c +++ b/arch/powerpc/platforms/powernv/setup.c @@ -243,6 +243,13 @@ static void pnv_kexec_cpu_down(int crash_shutdown, int secondary) } else { /* Primary waits for the secondaries to have reached OPAL */ pnv_kexec_wait_secondaries_down(); + + /* + * We might be running as little-endian - now that interrupts + * are disabled, reset the HILE bit to big-endian so we don't + * take interrupts in the wrong endian later + */ + opal_reinit_cpus(OPAL_REINIT_CPUS_HILE_BE); } } #endif /* CONFIG_KEXEC */
On powernv secondary cpus are returned to OPAL, and will then enter the target kernel in big-endian. However if it is set the HILE bit will persist, causing the first exception in the target kernel to be delivered in litte-endian regardless of the current endianess. If running on top of OPAL make sure the HILE bit is reset once we've finished waiting for all of the secondaries to be returned to OPAL. Signed-off-by: Samuel Mendoza-Jonas <sam.mj@au1.ibm.com> --- arch/powerpc/platforms/powernv/setup.c | 7 +++++++ 1 file changed, 7 insertions(+)