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Fri, 19 Jun 2015 12:49:44 +1000 (AEST) Authentication-Results: linaro.org; dkim=none (message not signed) header.d=none; Received: from snotra.am.freescale.net (192.88.168.50) by BLUPR03MB1475.namprd03.prod.outlook.com (10.163.81.17) with Microsoft SMTP Server (TLS) id 15.1.190.14; Fri, 19 Jun 2015 02:49:39 +0000 From: Scott Wood To: Mike Turquette , Tang Yuantian Subject: [RFC PATCH 6/8] cpufreq: qoriq: Remove frequency masking and minimum Date: Thu, 18 Jun 2015 21:49:16 -0500 Message-ID: <1434682158-7243-7-git-send-email-scottwood@freescale.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1434682158-7243-1-git-send-email-scottwood@freescale.com> References: <1434682158-7243-1-git-send-email-scottwood@freescale.com> MIME-Version: 1.0 X-Originating-IP: [192.88.168.50] X-ClientProxiedBy: BLUPR08CA0070.namprd08.prod.outlook.com (10.141.200.50) To BLUPR03MB1475.namprd03.prod.outlook.com (25.163.81.17) X-Microsoft-Exchange-Diagnostics: 1; BLUPR03MB1475; 2:YQH2/jh0hGuBKYZq48bfZhQKFEPcXNyVnr8nKHtCJ8mnF8q58JXQQfnH8THRxlmW; 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10:o5YvM/5CH+r98LQj5wLseSxZeo/pE9SB4vhSmhszoikdAGaWjmVePHusQpVdgpHs54Zlku7k4Y9NZ4Uo+d6jZ5wvbM+aI3wGC3QbCbgme5g=; 6:ZgJQKYXTFrsogURhG9iCJB7x+4bXKb5XExbLLWNCOM+0HlXtanYC9VZI0CeA7GV2 X-OriginatorOrg: freescale.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Jun 2015 02:49:39.4318 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-Transport-CrossTenantHeadersStamped: BLUPR03MB1475 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-pm@vger.kernel.org, "Rafael J. Wysocki" , Liberman Igal-B31950 , Scott Wood , linuxppc-dev@lists.ozlabs.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Bucur Madalin-Cristian-B32716 Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" The clock driver now takes care of ensuring that the mux only exposes options that are valid. The driver was currently being overly conservative in some cases -- for example, the "min_cpufreq = get_bus_freq()" restriction only applies to chips with erratum A-004510, and whether the freq_mask used on p5020 is needed depends on the actual frequencies of the PLLs (FWIW, p5040 has a similar limitation but its .freq_mask was zero). Further, the freq_mask mechanism makes assumptions about the number and order of the clock parents. The new driver does not adhere to those assumptions (in particular, it removes invalid options). Signed-off-by: Scott Wood --- drivers/cpufreq/qoriq-cpufreq.c | 92 +---------------------------------------- 1 file changed, 2 insertions(+), 90 deletions(-) diff --git a/drivers/cpufreq/qoriq-cpufreq.c b/drivers/cpufreq/qoriq-cpufreq.c index 32ab99e..514395f 100644 --- a/drivers/cpufreq/qoriq-cpufreq.c +++ b/drivers/cpufreq/qoriq-cpufreq.c @@ -36,53 +36,6 @@ struct cpu_data { struct cpufreq_frequency_table *table; }; -/** - * struct soc_data - SoC specific data - * @freq_mask: mask the disallowed frequencies - * @flag: unique flags - */ -struct soc_data { - u32 freq_mask[4]; - u32 flag; -}; - -#define FREQ_MASK 1 -/* see hardware specification for the allowed frqeuencies */ -static const struct soc_data sdata[] = { - { /* used by p2041 and p3041 */ - .freq_mask = {0x8, 0x8, 0x2, 0x2}, - .flag = FREQ_MASK, - }, - { /* used by p5020 */ - .freq_mask = {0x8, 0x2}, - .flag = FREQ_MASK, - }, - { /* used by p4080, p5040 */ - .freq_mask = {0}, - .flag = 0, - }, -}; - -/* - * the minimum allowed core frequency, in Hz - * for chassis v1.0, >= platform frequency - * for chassis v2.0, >= platform frequency / 2 - */ -static u32 min_cpufreq; -static const u32 *fmask; - -#if defined(CONFIG_ARM) -static int get_cpu_physical_id(int cpu) -{ - return topology_core_id(cpu); -} -#else -static int get_cpu_physical_id(int cpu) -{ - return get_hard_smp_processor_id(cpu); -} -#endif - static u32 get_bus_freq(void) { struct device_node *soc; @@ -195,7 +148,7 @@ static int qoriq_cpufreq_cpu_init(struct cpufreq_policy *policy) { struct device_node *np, *pnode; int i, count, ret; - u32 freq, mask; + u32 freq; struct clk *clk; struct cpufreq_frequency_table *table; struct cpu_data *data; @@ -230,23 +183,11 @@ static int qoriq_cpufreq_cpu_init(struct cpufreq_policy *policy) goto err_pclk; } - if (fmask) - mask = fmask[get_cpu_physical_id(cpu)]; - else - mask = 0x0; - for (i = 0; i < count; i++) { clk = clk_get_parent_by_index(policy->clk, i); data->pclk[i] = clk; freq = clk_get_rate(clk); - /* - * the clock is valid if its frequency is not masked - * and large than minimum allowed frequency. - */ - if (freq < min_cpufreq || (mask & (1 << i))) - table[i].frequency = CPUFREQ_ENTRY_INVALID; - else - table[i].frequency = freq / 1000; + table[i].frequency = freq / 1000; table[i].driver_data = i; } freq_table_redup(table, count); @@ -321,38 +262,9 @@ static struct cpufreq_driver qoriq_cpufreq_driver = { .attr = cpufreq_generic_attr, }; -static const struct of_device_id node_matches[] __initconst = { - { .compatible = "fsl,p2041-clockgen", .data = &sdata[0], }, - { .compatible = "fsl,p3041-clockgen", .data = &sdata[0], }, - { .compatible = "fsl,p5020-clockgen", .data = &sdata[1], }, - { .compatible = "fsl,p4080-clockgen", .data = &sdata[2], }, - { .compatible = "fsl,p5040-clockgen", .data = &sdata[2], }, - { .compatible = "fsl,qoriq-clockgen-2.0", }, - {} -}; - static int __init qoriq_cpufreq_init(void) { int ret; - struct device_node *np; - const struct of_device_id *match; - const struct soc_data *data; - - np = of_find_matching_node(NULL, node_matches); - if (!np) - return -ENODEV; - - match = of_match_node(node_matches, np); - data = match->data; - if (data) { - if (data->flag) - fmask = data->freq_mask; - min_cpufreq = get_bus_freq(); - } else { - min_cpufreq = get_bus_freq() / 2; - } - - of_node_put(np); ret = cpufreq_register_driver(&qoriq_cpufreq_driver); if (!ret)