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Ip=[192.88.158.2] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL2PR03MB370 Cc: Igal Liberman , afleming@gmail.com X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" From: Igal Liberman Signed-off-by: Igal Liberman --- arch/powerpc/boot/dts/fsl/b4si-post.dtsi | 11 +++++++++++ arch/powerpc/boot/dts/fsl/p2041si-post.dtsi | 8 ++++++++ arch/powerpc/boot/dts/fsl/p3041si-post.dtsi | 8 ++++++++ arch/powerpc/boot/dts/fsl/p4080si-post.dtsi | 16 ++++++++++++++++ arch/powerpc/boot/dts/fsl/p5020si-post.dtsi | 13 +++++++++++++ arch/powerpc/boot/dts/fsl/p5040si-post.dtsi | 26 ++++++++++++++++++++++++++ arch/powerpc/boot/dts/fsl/t1040si-post.dtsi | 8 ++++++++ arch/powerpc/boot/dts/fsl/t2081si-post.dtsi | 11 +++++++++++ arch/powerpc/boot/dts/fsl/t4240si-post.dtsi | 20 ++++++++++++++++++++ 9 files changed, 121 insertions(+) diff --git a/arch/powerpc/boot/dts/fsl/b4si-post.dtsi b/arch/powerpc/boot/dts/fsl/b4si-post.dtsi index f8c325e..38621ef 100644 --- a/arch/powerpc/boot/dts/fsl/b4si-post.dtsi +++ b/arch/powerpc/boot/dts/fsl/b4si-post.dtsi @@ -395,6 +395,17 @@ reg = <0xe0000 0xe00>; fsl,has-rstcr; fsl,liodn-bits = <12>; + + fm0clk: fm0-clk-mux { + #clock-cells = <0>; + compatible = "fsl,fman-clk-mux"; + clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>, <&pll0 3>, + <&platform_pll 0>, <&pll1 1>, <&pll1 2>; + clock-names = "pll0", "pll0-div2", "pll0-div3", + "pll0-div4", "platform-pll", "pll1-div2", + "pll1-div3"; + clock-output-names = "fm0-clk"; + }; }; /include/ "qoriq-clockgen2.dtsi" diff --git a/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi b/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi index 1f18b8b..60f63dc 100644 --- a/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi +++ b/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi @@ -316,6 +316,14 @@ fsl,has-rstcr; #sleep-cells = <1>; fsl,liodn-bits = <12>; + + fm0clk: fm0-clk-mux { + #clock-cells = <0>; + compatible = "fsl,fman-clk-mux"; + clocks = <&platform_pll 1>, <&pll1 1>; + clock-names = "platform-pll-div2", "pll1-div2"; + clock-output-names = "fm0-clk"; + }; }; pins: global-utilities@e0e00 { diff --git a/arch/powerpc/boot/dts/fsl/p3041si-post.dtsi b/arch/powerpc/boot/dts/fsl/p3041si-post.dtsi index a555d24..d4e6677 100644 --- a/arch/powerpc/boot/dts/fsl/p3041si-post.dtsi +++ b/arch/powerpc/boot/dts/fsl/p3041si-post.dtsi @@ -343,6 +343,14 @@ fsl,has-rstcr; #sleep-cells = <1>; fsl,liodn-bits = <12>; + + fm0clk: fm0-clk-mux { + #clock-cells = <0>; + compatible = "fsl,fman-clk-mux"; + clocks = <&platform_pll 1>, <&pll1 1>; + clock-names = "platform-pll-div2", "pll1-div2"; + clock-output-names = "fm0-clk"; + }; }; pins: global-utilities@e0e00 { diff --git a/arch/powerpc/boot/dts/fsl/p4080si-post.dtsi b/arch/powerpc/boot/dts/fsl/p4080si-post.dtsi index 0fe7281..d1cb691 100644 --- a/arch/powerpc/boot/dts/fsl/p4080si-post.dtsi +++ b/arch/powerpc/boot/dts/fsl/p4080si-post.dtsi @@ -363,6 +363,22 @@ fsl,has-rstcr; #sleep-cells = <1>; fsl,liodn-bits = <12>; + + fm0clk: fm0-clk-mux { + #clock-cells = <0>; + compatible = "fsl,fman-clk-mux"; + clocks = <&platform_pll 1>, <&pll2 1>; + clock-names = "platform-pll-div2", "pll2-div2"; + clock-output-names = "fm0-clk"; + }; + + fm1clk: fm1-clk-mux { + #clock-cells = <0>; + compatible = "fsl,fman-clk-mux"; + clocks = <&platform_pll 1>, <&pll2 1>; + clock-names = "platform-pll-div2", "pll2-div2"; + clock-output-names = "fm1-clk"; + }; }; pins: global-utilities@e0e00 { diff --git a/arch/powerpc/boot/dts/fsl/p5020si-post.dtsi b/arch/powerpc/boot/dts/fsl/p5020si-post.dtsi index a34ca20..9f3049d 100644 --- a/arch/powerpc/boot/dts/fsl/p5020si-post.dtsi +++ b/arch/powerpc/boot/dts/fsl/p5020si-post.dtsi @@ -348,6 +348,15 @@ fsl,has-rstcr; #sleep-cells = <1>; fsl,liodn-bits = <12>; + + fm0clk: fm0-clk-mux { + #clock-cells = <0>; + compatible = "fsl,fman-clk-mux"; + clocks = <&platform_pll 1>, <&pll1 1>, <&pll1 2>; + clock-names = "platform-pll-div2", "pll1-div2", + "pll1-div4"; + clock-output-names = "fm0-clk"; + }; }; pins: global-utilities@e0e00 { @@ -359,6 +368,10 @@ /include/ "qoriq-clockgen1.dtsi" global-utilities@e1000 { compatible = "fsl,p5020-clockgen", "fsl,qoriq-clockgen-1.0"; + + pll1: pll1@820 { + clock-output-names = "pll1", "pll1-div2", "pll1-div4"; + }; }; rcpm: global-utilities@e2000 { diff --git a/arch/powerpc/boot/dts/fsl/p5040si-post.dtsi b/arch/powerpc/boot/dts/fsl/p5040si-post.dtsi index bf57513..3dea4b6 100644 --- a/arch/powerpc/boot/dts/fsl/p5040si-post.dtsi +++ b/arch/powerpc/boot/dts/fsl/p5040si-post.dtsi @@ -308,6 +308,24 @@ fsl,has-rstcr; #sleep-cells = <1>; fsl,liodn-bits = <12>; + + fm0clk: fm0-clk-mux { + #clock-cells = <0>; + compatible = "fsl,fman-clk-mux"; + clocks = <&platform_pll 1>, <&pll2 1>, <&pll2 2>; + clock-names = "platform-pll-div2", "pll2-div2", + "pll2-div4"; + clock-output-names = "fm0-clk"; + }; + + fm1clk: fm1-clk-mux { + #clock-cells = <0>; + compatible = "fsl,fman-clk-mux"; + clocks = <&platform_pll 1>, <&pll2 1>, <&pll2 2>; + clock-names = "platform-pll-div2", "pll2-div2", + "pll2-div4"; + clock-output-names = "fm1-clk"; + }; }; pins: global-utilities@e0e00 { @@ -320,6 +338,14 @@ global-utilities@e1000 { compatible = "fsl,p5040-clockgen", "fsl,qoriq-clockgen-1.0"; + pll2: pll2@840 { + #clock-cells = <1>; + reg = <0x840 0x4>; + compatible = "fsl,qoriq-core-pll-1.0"; + clocks = <&sysclk>; + clock-output-names = "pll2", "pll2-div2", "pll2-div4"; + }; + mux2: mux2@40 { #clock-cells = <0>; reg = <0x40 0x4>; diff --git a/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi b/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi index 4d41ce1..8f718c6 100644 --- a/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi +++ b/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi @@ -418,6 +418,14 @@ reg = <0xe0000 0xe00>; fsl,has-rstcr; fsl,liodn-bits = <12>; + + fm0clk: fm0-clk-mux { + #clock-cells = <0>; + compatible = "fsl,fman-clk-mux"; + clocks = <&platform_pll 0>; + clock-names = "platform-pll"; + clock-output-names = "fm0-clk"; + }; }; /include/ "qoriq-clockgen2.dtsi" diff --git a/arch/powerpc/boot/dts/fsl/t2081si-post.dtsi b/arch/powerpc/boot/dts/fsl/t2081si-post.dtsi index c2cb0f3..06e76ec 100644 --- a/arch/powerpc/boot/dts/fsl/t2081si-post.dtsi +++ b/arch/powerpc/boot/dts/fsl/t2081si-post.dtsi @@ -530,6 +530,17 @@ reg = <0xe0000 0xe00>; fsl,has-rstcr; fsl,liodn-bits = <12>; + + fm0clk: fm0-clk-mux { + #clock-cells = <0>; + compatible = "fsl,fman-clk-mux"; + clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>, <&pll0 3>, + <&platform_pll 0>, <&pll1 1>, <&pll1 2>; + clock-names = "pll0", "pll0-div2", "pll0-div3", + "pll0-div4", "platform-pll", "pll1-div2", + "pll1-div3"; + clock-output-names = "fm0-clk"; + }; }; /include/ "qoriq-clockgen2.dtsi" diff --git a/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi b/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi index c18245e..5ef5ff0 100644 --- a/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi +++ b/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi @@ -945,6 +945,26 @@ reg = <0xe0000 0xe00>; fsl,has-rstcr; fsl,liodn-bits = <12>; + + fm0clk: fm0-clk-mux { + #clock-cells = <0>; + compatible = "fsl,fman-clk-mux"; + clocks = <&pll0 1>, <&pll0 2>, <&pll0 3>, + <&platform_pll 0>, <&pll1 1>; + clock-names = "pll0-div2", "pll0-div3", "pll0-div4", + "platform-pll", "pll1-div2"; + clock-output-names = "fm0-clk"; + }; + + fm1clk: fm1-clk-mux { + #clock-cells = <0>; + compatible = "fsl,fman-clk-mux"; + clocks = <&pll1 1>, <&pll1 2>, <&pll1 3>, + <&platform_pll 0>, <&pll0 1>, <&pll0 2>; + clock-names = "pll1-div2", "pll1-div3", "pll1-div4", + "platform-pll", "pll0-div2", "pll0-div3"; + clock-output-names = "fm1-clk"; + }; }; /include/ "qoriq-clockgen2.dtsi"