From patchwork Wed Feb 4 06:47:01 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dongsheng Wang X-Patchwork-Id: 436163 X-Patchwork-Delegate: scottwood@freescale.com Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 1813114021A for ; Wed, 4 Feb 2015 18:05:05 +1100 (AEDT) Received: from ozlabs.org (ozlabs.org [103.22.144.67]) by lists.ozlabs.org (Postfix) with ESMTP id F3F111A0F6A for ; Wed, 4 Feb 2015 18:05:04 +1100 (AEDT) X-Original-To: linuxppc-dev@lists.ozlabs.org Delivered-To: linuxppc-dev@lists.ozlabs.org Received: from na01-bn1-obe.outbound.protection.outlook.com (mail-bn1bon0138.outbound.protection.outlook.com [157.56.111.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3E57F1A09D9 for ; Wed, 4 Feb 2015 18:04:30 +1100 (AEDT) Received: from BY2PR03CA012.namprd03.prod.outlook.com (10.255.93.29) by BLUPR03MB182.namprd03.prod.outlook.com (10.255.212.148) with Microsoft SMTP Server (TLS) id 15.1.65.19; Wed, 4 Feb 2015 06:49:47 +0000 Received: from BN1BFFO11FD005.protection.gbl (10.255.93.4) by BY2PR03CA012.outlook.office365.com (10.255.93.29) with Microsoft SMTP Server (TLS) id 15.1.75.20 via Frontend Transport; Wed, 4 Feb 2015 06:49:46 +0000 Received: from az84smr01.freescale.net (192.88.158.2) by BN1BFFO11FD005.mail.protection.outlook.com (10.58.144.68) with Microsoft SMTP Server (TLS) id 15.1.87.10 via Frontend Transport; Wed, 4 Feb 2015 06:49:45 +0000 Received: from titan.ap.freescale.net ([10.192.208.233]) by az84smr01.freescale.net (8.14.3/8.14.0) with ESMTP id t146ngrR028995; Tue, 3 Feb 2015 23:49:43 -0700 From: Dongsheng Wang To: Subject: [PATCH] powerpc/fsl: add power_off support for fsl platform Date: Wed, 4 Feb 2015 14:47:01 +0800 Message-ID: <1423032421-31561-1-git-send-email-dongsheng.wang@freescale.com> X-Mailer: git-send-email 2.1.0.27.g96db324 X-EOPAttributedMessage: 0 Received-SPF: Fail (protection.outlook.com: domain of freescale.com does not designate 192.88.158.2 as permitted sender) receiver=protection.outlook.com; client-ip=192.88.158.2; helo=az84smr01.freescale.net; Authentication-Results: spf=fail (sender IP is 192.88.158.2) smtp.mailfrom=dongsheng.wang@freescale.com; freescale.mail.onmicrosoft.com; dkim=none (message not signed) header.d=none; X-Forefront-Antispam-Report: CIP:192.88.158.2; CTRY:US; IPV:NLI; EFV:NLI; SFV:NSPM; SFS:(10019020)(979002)(6009001)(339900001)(199003)(189002)(77096005)(77156002)(62966003)(87936001)(85426001)(450100001)(2371004)(50986999)(105606002)(229853001)(110136001)(48376002)(104016003)(33646002)(46102003)(50226001)(92566002)(19580395003)(36756003)(86362001)(2351001)(6806004)(50466002)(106466001)(47776003)(19580405001)(969003)(989001)(999001)(1009001)(1019001); DIR:OUT; SFP:1102; SCL:1; SRVR:BLUPR03MB182; H:az84smr01.freescale.net; FPR:; SPF:Fail; MLV:ovrnspm; PTR:InfoDomainNonexistent; A:1; MX:1; LANG:en; MIME-Version: 1.0 X-Microsoft-Antispam: UriScan:; X-Microsoft-Antispam: BCL:0;PCL:0;RULEID:;SRVR:BLUPR03MB182; X-Exchange-Antispam-Report-Test: UriScan:; X-Exchange-Antispam-Report-CFA-Test: BCL:0; PCL:0; RULEID:(601004); SRVR:BLUPR03MB182; X-Forefront-PRVS: 04772EA191 X-Exchange-Antispam-Report-CFA-Test: BCL:0;PCL:0;RULEID:;SRVR:BLUPR03MB182; X-OriginatorOrg: freescale.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Feb 2015 06:49:45.9666 (UTC) X-MS-Exchange-CrossTenant-Id: 710a03f5-10f6-4d38-9ff4-a80b81da590d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=710a03f5-10f6-4d38-9ff4-a80b81da590d; Ip=[192.88.158.2] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BLUPR03MB182 Cc: linuxppc-dev@lists.ozlabs.org, hongtao.jia@freescale.com, Wang Dongsheng , jason.jin@freescale.com X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" From: Wang Dongsheng QIXIS System Logic FPGA support to manage system power. So we through QIXIS to power off freescale SOC. Signed-off-by: Wang Dongsheng diff --git a/arch/powerpc/platforms/85xx/corenet_generic.c b/arch/powerpc/platforms/85xx/corenet_generic.c index 1f309cc..e1a1eb5 100644 --- a/arch/powerpc/platforms/85xx/corenet_generic.c +++ b/arch/powerpc/platforms/85xx/corenet_generic.c @@ -81,6 +81,8 @@ void __init corenet_gen_setup_arch(void) pr_info("%s board\n", ppc_md.name); mpc85xx_qe_init(); + + ppc_md_fixup(); } static const struct of_device_id of_device_ids[] = { diff --git a/arch/powerpc/sysdev/fsl_soc.c b/arch/powerpc/sysdev/fsl_soc.c index 99269c0..6de9f1b 100644 --- a/arch/powerpc/sysdev/fsl_soc.c +++ b/arch/powerpc/sysdev/fsl_soc.c @@ -215,6 +215,54 @@ void fsl_rstcr_restart(char *cmd) } #endif +#define QIXIS_PWR_CTL2 0x21 +#define QIXIS_PWR_CTL2_PWR 0x80 +static void fsl_power_off(void) +{ + struct device_node *pixis_node; + void __iomem *pixis; + u32 pwroff_offset, value; + + pixis_node = of_find_compatible_node(NULL, NULL, "fsl,fpga-qixis"); + if (!pixis_node) { + pr_err("%s: Missing pixis node\n", __func__); + return; + } + + pwroff_offset = QIXIS_PWR_CTL2; + value = QIXIS_PWR_CTL2_PWR; + + pixis = of_iomap(pixis_node, 0); + of_node_put(pixis_node); + if (!pixis) { + pr_err("%s: Could not map pixis registers\n", __func__); + return; + } + + local_irq_disable(); + + setbits8(pixis + pwroff_offset, value); + + iounmap(pixis); + + while (1) + ; +} + +void ppc_md_fixup(void) +{ + struct device_node *np; + + np = of_find_compatible_node(NULL, NULL, "fsl,fpga-qixis"); + if (!np) + return; + + of_node_put(np); + + pm_power_off = fsl_power_off; + ppc_md.halt = fsl_power_off; +} + #if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE) struct platform_diu_data_ops diu_ops; EXPORT_SYMBOL(diu_ops); diff --git a/arch/powerpc/sysdev/fsl_soc.h b/arch/powerpc/sysdev/fsl_soc.h index 4c5a19e..ca90e24 100644 --- a/arch/powerpc/sysdev/fsl_soc.h +++ b/arch/powerpc/sysdev/fsl_soc.h @@ -21,6 +21,8 @@ struct device_node; extern void fsl_rstcr_restart(char *cmd); +void ppc_md_fixup(void); + /* The different ports that the DIU can be connected to */ enum fsl_diu_monitor_port { FSL_DIU_PORT_DVI, /* DVI */