From patchwork Thu Jan 15 06:03:41 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: tang yuantian X-Patchwork-Id: 429258 X-Patchwork-Delegate: scottwood@freescale.com Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id E7F94140281 for ; Thu, 15 Jan 2015 17:07:43 +1100 (AEDT) Received: from ozlabs.org (ozlabs.org [103.22.144.67]) by lists.ozlabs.org (Postfix) with ESMTP id 6D69F1A117E for ; Thu, 15 Jan 2015 17:07:43 +1100 (AEDT) X-Original-To: linuxppc-dev@lists.ozlabs.org Delivered-To: linuxppc-dev@lists.ozlabs.org Received: from na01-bl2-obe.outbound.protection.outlook.com (mail-bl2on0109.outbound.protection.outlook.com [65.55.169.109]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 92C0C1A0E02 for ; Thu, 15 Jan 2015 17:06:14 +1100 (AEDT) Received: from BY2PR03CA011.namprd03.prod.outlook.com (10.255.93.28) by BY2PR03MB571.namprd03.prod.outlook.com (10.141.143.145) with Microsoft SMTP Server (TLS) id 15.1.53.17; Thu, 15 Jan 2015 06:06:07 +0000 Received: from BN1BFFO11FD040.protection.gbl (10.255.93.4) by BY2PR03CA011.outlook.office365.com (10.255.93.28) with Microsoft SMTP Server (TLS) id 15.1.59.20 via Frontend Transport; Thu, 15 Jan 2015 06:06:06 +0000 Received: from az84smr01.freescale.net (192.88.158.2) by BN1BFFO11FD040.mail.protection.outlook.com (10.58.144.103) with Microsoft SMTP Server (TLS) id 15.1.49.13 via Frontend Transport; Thu, 15 Jan 2015 06:06:06 +0000 Received: from titan.ap.freescale.net ([10.192.208.233]) by az84smr01.freescale.net (8.14.3/8.14.0) with ESMTP id t0F65qXQ008564; Wed, 14 Jan 2015 23:06:04 -0700 From: To: Subject: [PATCH 2/2] clk: ppc-corenet: rename driver to clk-qoriq Date: Thu, 15 Jan 2015 14:03:41 +0800 Message-ID: <1421301821-18917-2-git-send-email-Yuantian.Tang@freescale.com> X-Mailer: git-send-email 2.1.0.27.g96db324 In-Reply-To: <1421301821-18917-1-git-send-email-Yuantian.Tang@freescale.com> References: <1421301821-18917-1-git-send-email-Yuantian.Tang@freescale.com> X-EOPAttributedMessage: 0 Received-SPF: Fail (protection.outlook.com: domain of freescale.com does not designate 192.88.158.2 as permitted sender) receiver=protection.outlook.com; client-ip=192.88.158.2; helo=az84smr01.freescale.net; Authentication-Results: spf=fail (sender IP is 192.88.158.2) smtp.mailfrom=Yuantian.Tang@freescale.com; X-Forefront-Antispam-Report: CIP:192.88.158.2; CTRY:US; IPV:NLI; EFV:NLI; SFV:NSPM; SFS:(10019020)(6009001)(339900001)(199003)(189002)(85426001)(81156004)(106466001)(19580405001)(6806004)(19580395003)(69596002)(86152002)(97736003)(86362001)(50226001)(2351001)(229853001)(46102003)(87936001)(110136001)(105606002)(50986999)(76176999)(50466002)(48376002)(104016003)(47776003)(36756003)(64706001)(92566002)(77096005)(68736005)(62966003)(2950100001)(77156002)(2004002); DIR:OUT; SFP:1102; SCL:1; SRVR:BY2PR03MB571; H:az84smr01.freescale.net; FPR:; SPF:Fail; MLV:sfv; PTR:InfoDomainNonexistent; A:1; MX:1; LANG:en; MIME-Version: 1.0 X-DmarcAction-Test: None X-Microsoft-Antispam: UriScan:; X-Microsoft-Antispam: BCL:0;PCL:0;RULEID:(3005004);SRVR:BY2PR03MB571; X-Exchange-Antispam-Report-Test: UriScan:; X-Exchange-Antispam-Report-CFA-Test: BCL:0; PCL:0; RULEID:(601004); SRVR:BY2PR03MB571; X-Forefront-PRVS: 0457F11EAF X-Exchange-Antispam-Report-CFA-Test: BCL:0;PCL:0;RULEID:;SRVR:BY2PR03MB571; X-OriginatorOrg: freescale.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Jan 2015 06:06:06.5914 (UTC) X-MS-Exchange-CrossTenant-Id: 710a03f5-10f6-4d38-9ff4-a80b81da590d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=710a03f5-10f6-4d38-9ff4-a80b81da590d; Ip=[192.88.158.2] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY2PR03MB571 Cc: b07421@freescale.com, linuxppc-dev@lists.ozlabs.org, Tang Yuantian X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" From: Tang Yuantian Freescale introduced new ARM-based socs which using the compatible clock IP block with PowerPC-based socs'. So this driver can be used on both platforms. Updated relevant descriptions and renamed this driver to better represent its meaning and keep the function of driver untouched. Signed-off-by: Tang Yuantian --- Documentation/devicetree/bindings/clock/qoriq-clock.txt | 5 +++-- drivers/clk/Kconfig | 10 +++++----- drivers/clk/Makefile | 2 +- drivers/clk/{clk-ppc-corenet.c => clk-qoriq.c} | 6 +++--- drivers/cpufreq/Kconfig.powerpc | 2 +- 5 files changed, 13 insertions(+), 12 deletions(-) rename drivers/clk/{clk-ppc-corenet.c => clk-qoriq.c} (98%) diff --git a/Documentation/devicetree/bindings/clock/qoriq-clock.txt b/Documentation/devicetree/bindings/clock/qoriq-clock.txt index 266ff9d..df4a259 100644 --- a/Documentation/devicetree/bindings/clock/qoriq-clock.txt +++ b/Documentation/devicetree/bindings/clock/qoriq-clock.txt @@ -1,6 +1,6 @@ -* Clock Block on Freescale CoreNet Platforms +* Clock Block on Freescale QorIQ Platforms -Freescale CoreNet chips take primary clocking input from the external +Freescale qoriq chips take primary clocking input from the external SYSCLK signal. The SYSCLK input (frequency) is multiplied using multiple phase locked loops (PLL) to create a variety of frequencies which can then be passed to a variety of internal logic, including @@ -29,6 +29,7 @@ Required properties: * "fsl,t4240-clockgen" * "fsl,b4420-clockgen" * "fsl,b4860-clockgen" + * "fsl,ls1021a-clockgen" Chassis clock strings include: * "fsl,qoriq-clockgen-1.0": for chassis 1.0 clocks * "fsl,qoriq-clockgen-2.0": for chassis 2.0 clocks diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index 3f44f29..a896fbc 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -101,12 +101,12 @@ config COMMON_CLK_AXI_CLKGEN Support for the Analog Devices axi-clkgen pcore clock generator for Xilinx FPGAs. It is commonly used in Analog Devices' reference designs. -config CLK_PPC_CORENET - bool "Clock driver for PowerPC corenet platforms" - depends on PPC_E500MC && OF +config CLK_QORIQ + bool "Clock driver for Freescale QorIQ platforms" + depends on (PPC_E500MC || ARM) && OF ---help--- - This adds the clock driver support for Freescale PowerPC corenet - platforms using common clock framework. + This adds the clock driver support for Freescale QorIQ platforms + using common clock framework. config COMMON_CLK_XGENE bool "Clock driver for APM XGene SoC" diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index d5fba5b..4ff94cd 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -30,7 +30,7 @@ obj-$(CONFIG_ARCH_MOXART) += clk-moxart.o obj-$(CONFIG_ARCH_NOMADIK) += clk-nomadik.o obj-$(CONFIG_ARCH_NSPIRE) += clk-nspire.o obj-$(CONFIG_COMMON_CLK_PALMAS) += clk-palmas.o -obj-$(CONFIG_CLK_PPC_CORENET) += clk-ppc-corenet.o +obj-$(CONFIG_CLK_QORIQ) += clk-qoriq.o obj-$(CONFIG_COMMON_CLK_RK808) += clk-rk808.o obj-$(CONFIG_COMMON_CLK_S2MPS11) += clk-s2mps11.o obj-$(CONFIG_COMMON_CLK_SI5351) += clk-si5351.o diff --git a/drivers/clk/clk-ppc-corenet.c b/drivers/clk/clk-qoriq.c similarity index 98% rename from drivers/clk/clk-ppc-corenet.c rename to drivers/clk/clk-qoriq.c index 5e9bb18..f9b7eb4 100644 --- a/drivers/clk/clk-ppc-corenet.c +++ b/drivers/clk/clk-qoriq.c @@ -5,7 +5,7 @@ * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. * - * clock driver for Freescale PowerPC corenet SoCs. + * clock driver for Freescale QorIQ SoCs. */ #include #include @@ -166,7 +166,7 @@ static void __init core_pll_init(struct device_node *np) base = of_iomap(np, 0); if (!base) { - pr_err("clk-ppc: iomap error\n"); + pr_err("clk-qoriq: iomap error\n"); return; } @@ -260,7 +260,7 @@ static void __init sysclk_init(struct device_node *node) u32 rate; if (!np) { - pr_err("ppc-clk: could not get parent node\n"); + pr_err("qoriq-clk: could not get parent node\n"); return; } diff --git a/drivers/cpufreq/Kconfig.powerpc b/drivers/cpufreq/Kconfig.powerpc index 72564b7..7ea2441 100644 --- a/drivers/cpufreq/Kconfig.powerpc +++ b/drivers/cpufreq/Kconfig.powerpc @@ -26,7 +26,7 @@ config CPU_FREQ_MAPLE config PPC_CORENET_CPUFREQ tristate "CPU frequency scaling driver for Freescale E500MC SoCs" depends on PPC_E500MC && OF && COMMON_CLK - select CLK_PPC_CORENET + select CLK_QORIQ help This adds the CPUFreq driver support for Freescale e500mc, e5500 and e6500 series SoCs which are capable of changing