From patchwork Thu Jan 15 06:03:40 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: tang yuantian X-Patchwork-Id: 429257 X-Patchwork-Delegate: scottwood@freescale.com Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 2E9E014027F for ; Thu, 15 Jan 2015 17:06:39 +1100 (AEDT) Received: from ozlabs.org (ozlabs.org [103.22.144.67]) by lists.ozlabs.org (Postfix) with ESMTP id 201201A0DBF for ; Thu, 15 Jan 2015 17:06:39 +1100 (AEDT) X-Original-To: linuxppc-dev@lists.ozlabs.org Delivered-To: linuxppc-dev@lists.ozlabs.org Received: from na01-bl2-obe.outbound.protection.outlook.com (mail-bl2on0130.outbound.protection.outlook.com [65.55.169.130]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id AED4A1A0C76 for ; Thu, 15 Jan 2015 17:06:05 +1100 (AEDT) Received: from DM2PR03MB575.namprd03.prod.outlook.com (10.141.84.151) by DM2PR03MB510.namprd03.prod.outlook.com (10.141.87.15) with Microsoft SMTP Server (TLS) id 15.1.53.17; Thu, 15 Jan 2015 06:05:58 +0000 Received: from BY2PR03CA061.namprd03.prod.outlook.com (10.141.249.34) by DM2PR03MB575.namprd03.prod.outlook.com (10.141.84.151) with Microsoft SMTP Server (TLS) id 15.1.53.17; Thu, 15 Jan 2015 06:05:57 +0000 Received: from BL2FFO11FD055.protection.gbl (2a01:111:f400:7c09::121) by BY2PR03CA061.outlook.office365.com (2a01:111:e400:2c5d::34) with Microsoft SMTP Server (TLS) id 15.1.53.17 via Frontend Transport; Thu, 15 Jan 2015 06:05:56 +0000 Received: from az84smr01.freescale.net (192.88.158.2) by BL2FFO11FD055.mail.protection.outlook.com (10.173.161.183) with Microsoft SMTP Server (TLS) id 15.1.49.13 via Frontend Transport; Thu, 15 Jan 2015 06:05:55 +0000 Received: from titan.ap.freescale.net ([10.192.208.233]) by az84smr01.freescale.net (8.14.3/8.14.0) with ESMTP id t0F65qXP008564; Wed, 14 Jan 2015 23:05:53 -0700 From: To: Subject: [PATCH 1/2] clock: redefine variable clocks_per_pll as a struct member Date: Thu, 15 Jan 2015 14:03:40 +0800 Message-ID: <1421301821-18917-1-git-send-email-Yuantian.Tang@freescale.com> X-Mailer: git-send-email 2.1.0.27.g96db324 X-EOPAttributedMessage: 0 Received-SPF: Fail (protection.outlook.com: domain of freescale.com does not designate 192.88.158.2 as permitted sender) receiver=protection.outlook.com; client-ip=192.88.158.2; helo=az84smr01.freescale.net; Authentication-Results: spf=fail (sender IP is 192.88.158.2) smtp.mailfrom=Yuantian.Tang@freescale.com; X-Forefront-Antispam-Report: CIP:192.88.158.2; CTRY:US; IPV:NLI; EFV:NLI; SFV:NSPM; SFS:(10019020)(6009001)(339900001)(189002)(199003)(97736003)(50226001)(86152002)(50986999)(77156002)(62966003)(36756003)(92566002)(47776003)(64706001)(229853001)(2351001)(106466001)(48376002)(81156004)(6806004)(104016003)(19580395003)(86362001)(69596002)(19580405001)(105606002)(68736005)(46102003)(77096005)(110136001)(50466002)(87936001)(85426001)(15975445007); DIR:OUT; SFP:1102; SCL:1; SRVR:DM2PR03MB575; H:az84smr01.freescale.net; FPR:; SPF:Fail; MLV:sfv; PTR:InfoDomainNonexistent; MX:1; A:1; LANG:en; MIME-Version: 1.0 X-DmarcAction-Test: None X-Microsoft-Antispam: UriScan:;UriScan:; X-Microsoft-Antispam: BCL:0;PCL:0;RULEID:(3005004);SRVR:DM2PR03MB575; X-Exchange-Antispam-Report-Test: UriScan:; X-Exchange-Antispam-Report-CFA-Test: BCL:0; PCL:0; RULEID:(601004); SRVR:DM2PR03MB575; X-Forefront-PRVS: 0457F11EAF X-Exchange-Antispam-Report-CFA-Test: BCL:0;PCL:0;RULEID:;SRVR:DM2PR03MB575; X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Jan 2015 06:05:55.8536 (UTC) X-MS-Exchange-CrossTenant-Id: 710a03f5-10f6-4d38-9ff4-a80b81da590d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=710a03f5-10f6-4d38-9ff4-a80b81da590d; Ip=[192.88.158.2] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM2PR03MB575 X-Microsoft-Antispam: BCL:0;PCL:0;RULEID:;SRVR:DM2PR03MB510; X-OriginatorOrg: freescale.com Cc: b07421@freescale.com, linuxppc-dev@lists.ozlabs.org, Tang Yuantian X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" From: Tang Yuantian redefine variable clocks_per_pll as a struct member If there are multiple PLL clock nodes, this variable will get overwritten. Redefining it as a struct member can avoid that. Signed-off-by: Tang Yuantian --- These patches are based on following three patches which are acked by Scott wood : 1. http://patchwork.ozlabs.org/patch/417292/ Revert "clk: ppc-corenet: Fix Section mismatch warning" 2. http://patchwork.ozlabs.org/patch/417295/ powerpc: call of_clk_init() from time_init() 3. http://patchwork.ozlabs.org/patch/417297/ clk: ppc-corenet: fix section mismatch warning drivers/clk/clk-ppc-corenet.c | 22 +++++++++++++++------- 1 file changed, 15 insertions(+), 7 deletions(-) diff --git a/drivers/clk/clk-ppc-corenet.c b/drivers/clk/clk-ppc-corenet.c index 57a2de4..5e9bb18 100644 --- a/drivers/clk/clk-ppc-corenet.c +++ b/drivers/clk/clk-ppc-corenet.c @@ -19,6 +19,7 @@ struct cmux_clk { struct clk_hw hw; void __iomem *reg; + unsigned int clk_per_pll; u32 flags; }; @@ -27,14 +28,12 @@ struct cmux_clk { #define CLKSEL_ADJUST BIT(0) #define to_cmux_clk(p) container_of(p, struct cmux_clk, hw) -static unsigned int clocks_per_pll; - static int cmux_set_parent(struct clk_hw *hw, u8 idx) { struct cmux_clk *clk = to_cmux_clk(hw); u32 clksel; - clksel = ((idx / clocks_per_pll) << 2) + idx % clocks_per_pll; + clksel = ((idx / clk->clk_per_pll) << 2) + idx % clk->clk_per_pll; if (clk->flags & CLKSEL_ADJUST) clksel += 8; clksel = (clksel & 0xf) << CLKSEL_SHIFT; @@ -52,7 +51,7 @@ static u8 cmux_get_parent(struct clk_hw *hw) clksel = (clksel >> CLKSEL_SHIFT) & 0xf; if (clk->flags & CLKSEL_ADJUST) clksel -= 8; - clksel = (clksel >> 2) * clocks_per_pll + clksel % 4; + clksel = (clksel >> 2) * clk->clk_per_pll + clksel % 4; return clksel; } @@ -72,6 +71,7 @@ static void __init core_mux_init(struct device_node *np) u32 offset; const char *clk_name; const char **parent_names; + struct of_phandle_args clkspec; rc = of_property_read_u32(np, "reg", &offset); if (rc) { @@ -105,6 +105,17 @@ static void __init core_mux_init(struct device_node *np) goto err_clk; } + rc = of_parse_phandle_with_args(np, "clocks", "#clock-cells", 0, + &clkspec); + if (rc) { + pr_err("%s: parse clock node error\n", __func__); + goto err_clk; + } + + cmux_clk->clk_per_pll = of_property_count_strings(clkspec.np, + "clock-output-names"); + of_node_put(clkspec.np); + node = of_find_compatible_node(NULL, NULL, "fsl,p4080-clockgen"); if (node && (offset >= 0x80)) cmux_clk->flags = CLKSEL_ADJUST; @@ -181,9 +192,6 @@ static void __init core_pll_init(struct device_node *np) goto err_map; } - /* output clock number per PLL */ - clocks_per_pll = count; - subclks = kzalloc(sizeof(struct clk *) * count, GFP_KERNEL); if (!subclks) { pr_err("%s: could not allocate subclks\n", __func__);