From patchwork Thu Jul 24 01:44:28 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Scott Wood X-Patchwork-Id: 373083 X-Patchwork-Delegate: scottwood@freescale.com Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 68A061401A0 for ; Thu, 24 Jul 2014 11:45:24 +1000 (EST) Received: from ozlabs.org (ozlabs.org [103.22.144.67]) by lists.ozlabs.org (Postfix) with ESMTP id 413461A094D for ; Thu, 24 Jul 2014 11:45:24 +1000 (EST) X-Original-To: linuxppc-dev@lists.ozlabs.org Delivered-To: linuxppc-dev@lists.ozlabs.org Received: from na01-by2-obe.outbound.protection.outlook.com (mail-by2lp0236.outbound.protection.outlook.com [207.46.163.236]) (using TLSv1 with cipher ECDHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 44E901A0186 for ; Thu, 24 Jul 2014 11:44:44 +1000 (EST) Received: from snotra.am.freescale.net (192.88.168.50) by CY1PR0301MB0729.namprd03.prod.outlook.com (25.160.159.147) with Microsoft SMTP Server (TLS) id 15.0.995.14; Thu, 24 Jul 2014 01:44:35 +0000 From: Scott Wood To: Subject: [PATCH 1/2] powerpc/booke: Define MSR bits the same way as reg.h Date: Wed, 23 Jul 2014 20:44:28 -0500 Message-ID: <1406166269-22796-1-git-send-email-scottwood@freescale.com> X-Mailer: git-send-email 1.9.1 MIME-Version: 1.0 X-Originating-IP: [192.88.168.50] X-ClientProxiedBy: BLUPR05CA0052.namprd05.prod.outlook.com (10.141.20.22) To CY1PR0301MB0729.namprd03.prod.outlook.com (25.160.159.147) X-Microsoft-Antispam: BCL:0;PCL:0;RULEID: X-Forefront-PRVS: 028256169F X-Forefront-Antispam-Report: SFV:NSPM; SFS:(6009001)(189002)(199002)(50466002)(79102001)(105586002)(110136001)(66066001)(85306003)(77096002)(95666004)(99396002)(102836001)(81342001)(74662001)(74502001)(46102001)(81542001)(80022001)(2351001)(20776003)(229853001)(64706001)(107046002)(47776003)(42186005)(50986999)(50226001)(4396001)(31966008)(76482001)(106356001)(77982001)(101416001)(87286001)(86362001)(93916002)(62966002)(77156001)(36756003)(83322001)(83072002)(88136002)(19580395003)(89996001)(19580405001)(87976001)(21056001)(92566001)(85852003)(104166001)(33646002)(48376002)(92726001); DIR:OUT; SFP:; SCL:1; SRVR:CY1PR0301MB0729; H:snotra.am.freescale.net; FPR:; MLV:sfv; PTR:InfoNoRecords; MX:1; LANG:en; X-OriginatorOrg: freescale.com Cc: Scott Wood X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" This ensures that all MSR definitions are consistently unsigned long, and that MSR_CM does not become 0xffffffff80000000 (this is usually harmless because MSR is 32-bit on booke and is mainly noticeable when debugging, but still I'd rather avoid it). Signed-off-by: Scott Wood --- arch/powerpc/include/asm/reg_booke.h | 28 +++++++++++++++++++--------- 1 file changed, 19 insertions(+), 9 deletions(-) diff --git a/arch/powerpc/include/asm/reg_booke.h b/arch/powerpc/include/asm/reg_booke.h index 6148292..da42982 100644 --- a/arch/powerpc/include/asm/reg_booke.h +++ b/arch/powerpc/include/asm/reg_booke.h @@ -16,15 +16,25 @@ #define __ASM_POWERPC_REG_BOOKE_H__ /* Machine State Register (MSR) Fields */ -#define MSR_GS (1<<28) /* Guest state */ -#define MSR_UCLE (1<<26) /* User-mode cache lock enable */ -#define MSR_SPE (1<<25) /* Enable SPE */ -#define MSR_DWE (1<<10) /* Debug Wait Enable */ -#define MSR_UBLE (1<<10) /* BTB lock enable (e500) */ -#define MSR_IS MSR_IR /* Instruction Space */ -#define MSR_DS MSR_DR /* Data Space */ -#define MSR_PMM (1<<2) /* Performance monitor mark bit */ -#define MSR_CM (1<<31) /* Computation Mode (0=32-bit, 1=64-bit) */ +#define MSR_GS_LG 28 /* Guest state */ +#define MSR_UCLE_LG 26 /* User-mode cache lock enable */ +#define MSR_SPE_LG 25 /* Enable SPE */ +#define MSR_DWE_LG 10 /* Debug Wait Enable */ +#define MSR_UBLE_LG 10 /* BTB lock enable (e500) */ +#define MSR_IS_LG MSR_IR_LG /* Instruction Space */ +#define MSR_DS_LG MSR_DR_LG /* Data Space */ +#define MSR_PMM_LG 2 /* Performance monitor mark bit */ +#define MSR_CM_LG 31 /* Computation Mode (0=32-bit, 1=64-bit) */ + +#define MSR_GS __MASK(MSR_GS_LG) +#define MSR_UCLE __MASK(MSR_UCLE_LG) +#define MSR_SPE __MASK(MSR_SPE_LG) +#define MSR_DWE __MASK(MSR_DWE_LG) +#define MSR_UBLE __MASK(MSR_UBLE_LG) +#define MSR_IS __MASK(MSR_IS_LG) +#define MSR_DS __MASK(MSR_DS_LG) +#define MSR_PMM __MASK(MSR_PMM_LG) +#define MSR_CM __MASK(MSR_CM_LG) #if defined(CONFIG_PPC_BOOK3E_64) #define MSR_64BIT MSR_CM