From patchwork Tue Apr 15 07:43:19 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dongsheng Wang X-Patchwork-Id: 339185 Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from ozlabs.org (localhost [127.0.0.1]) by ozlabs.org (Postfix) with ESMTP id 89A431401A3 for ; Tue, 15 Apr 2014 17:47:09 +1000 (EST) Received: from co9outboundpool.messaging.microsoft.com (co9ehsobe001.messaging.microsoft.com [207.46.163.24]) (using TLSv1 with cipher AES128-SHA (128/128 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 086D2140151 for ; Tue, 15 Apr 2014 17:45:56 +1000 (EST) Received: from mail106-co9-R.bigfish.com (10.236.132.233) by CO9EHSOBE035.bigfish.com (10.236.130.98) with Microsoft SMTP Server id 14.1.225.22; Tue, 15 Apr 2014 07:45:15 +0000 Received: from mail106-co9 (localhost [127.0.0.1]) by mail106-co9-R.bigfish.com (Postfix) with ESMTP id A87E5200459 for ; Tue, 15 Apr 2014 07:45:14 +0000 (UTC) X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPV:NLI; H:mail.freescale.net; RD:none; EFVD:NLI X-SpamScore: 3 X-BigFish: VS3(zzzz1f42h2148h1ee6h1de0h1fdah2073h2146h1202h1e76h2189h1d1ah1d2ah21bch1fc6h208chzz1de098h8275bh1de097hz2dh2a8h839hd24he5bhf0ah1288h12a5h12a9h12bdh12e5h137ah139eh13b6h1441h1504h1537h162dh1631h1758h1898h18e1h1946h19b5h1ad9h1b0ah1b2fh2222h224fh1fb3h1d0ch1d2eh1d3fh1dfeh1dffh1e23h1fe8h1ff5h2218h2216h226dh22d0h24afh2327h2336h2438h2461h2487h24d7h2516h2545h255eh25cch25f6h2605h268bh26d3h10bek1155h) Received: from mail106-co9 (localhost.localdomain [127.0.0.1]) by mail106-co9 (MessageSwitch) id 1397547913118083_29197; Tue, 15 Apr 2014 07:45:13 +0000 (UTC) Received: from CO9EHSMHS022.bigfish.com (unknown [10.236.132.234]) by mail106-co9.bigfish.com (Postfix) with ESMTP id 0E1AC460040; Tue, 15 Apr 2014 07:45:13 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by CO9EHSMHS022.bigfish.com (10.236.130.32) with Microsoft SMTP Server (TLS) id 14.16.227.3; Tue, 15 Apr 2014 07:45:11 +0000 Received: from az84smr01.freescale.net (10.64.34.197) by 039-SN1MMR1-001.039d.mgd.msft.net (10.84.1.13) with Microsoft SMTP Server (TLS) id 14.3.174.2; Tue, 15 Apr 2014 07:45:46 +0000 Received: from titan.ap.freescale.net (udp143770uds.ap.freescale.net [10.192.208.233] (may be forged)) by az84smr01.freescale.net (8.14.3/8.14.0) with ESMTP id s3F7jZNe026573; Tue, 15 Apr 2014 00:45:44 -0700 From: Dongsheng Wang To: Subject: [PATCH 2/2] fsl/pci: fix EP device sometimes hangup when system resume from sleep Date: Tue, 15 Apr 2014 15:43:19 +0800 Message-ID: <1397547799-29464-2-git-send-email-dongsheng.wang@freescale.com> X-Mailer: git-send-email 1.8.5 In-Reply-To: <1397547799-29464-1-git-send-email-dongsheng.wang@freescale.com> References: <1397547799-29464-1-git-send-email-dongsheng.wang@freescale.com> MIME-Version: 1.0 X-OriginatorOrg: freescale.com X-FOPE-CONNECTOR: Id%0$Dn%*$RO%0$TLS%0$FQDN%$TlsDn% X-FOPE-CONNECTOR: Id%0$Dn%FREESCALE.MAIL.ONMICROSOFT.COM$RO%1$TLS%0$FQDN%$TlsDn% Cc: linuxppc-dev@lists.ozlabs.org, Wang Dongsheng , jason.jin@freescale.com X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.16 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" From: Wang Dongsheng Root cause is pcie power management state transition need a delay. The delay time define in "PCI Bus Power Management Interface Specification". D0, D1 or D2 --> D3 need to delay 10ms. D3 --> D0 need to delay 10ms. Signed-off-by: Wang Dongsheng diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c index 4bd091a..33950ad 100644 --- a/arch/powerpc/sysdev/fsl_pci.c +++ b/arch/powerpc/sysdev/fsl_pci.c @@ -1175,15 +1175,24 @@ static void send_pme_turnoff_message(struct pci_controller *hose) setbits32(&pci->pex_pmcr, PEX_PMCR_PTOMR); /* Wait trun off done */ - for (i = 0; i < 150; i++) { + /* RC will get this detect quickly */ + for (i = 0; i < 50; i++) { dr = in_be32(&pci->pex_pme_mes_dr); - if (dr) { + if (dr & ENL23_DETECT_BIT) { out_be32(&pci->pex_pme_mes_dr, dr); break; } udelay(1000); } + + /* + * "PCI Bus Power Management Interface Specification" define + * Minimum System Software Guaranteed Delays + * + * D0, D1 or D2 --> D3, need delay 10ms. + */ + mdelay(10); } static void fsl_pci_syscore_do_suspend(struct pci_controller *hose) @@ -1211,9 +1220,10 @@ static void fsl_pci_syscore_do_resume(struct pci_controller *hose) setbits32(&pci->pex_pmcr, PEX_PMCR_EXL2S); /* Wait exit done */ - for (i = 0; i < 150; i++) { + /* RC will get this detect quickly */ + for (i = 0; i < 50; i++) { dr = in_be32(&pci->pex_pme_mes_dr); - if (dr) { + if (dr & EXL23_DETECT_BIT) { out_be32(&pci->pex_pme_mes_dr, dr); break; } @@ -1221,6 +1231,14 @@ static void fsl_pci_syscore_do_resume(struct pci_controller *hose) udelay(1000); } + /* + * "PCI Bus Power Management Interface Specification" define + * Minimum System Software Guaranteed Delays + * + * D3 hot --> D0, need delay 10ms. + */ + mdelay(10); + setup_pci_atmu(hose); } diff --git a/arch/powerpc/sysdev/fsl_pci.h b/arch/powerpc/sysdev/fsl_pci.h index c1cec77..37fc644 100644 --- a/arch/powerpc/sysdev/fsl_pci.h +++ b/arch/powerpc/sysdev/fsl_pci.h @@ -39,6 +39,9 @@ struct platform_device; #define PME_DISR_EN_ENL23D 0x00002000 #define PME_DISR_EN_EXL23D 0x00001000 +#define ENL23_DETECT_BIT 0x00002000 +#define EXL23_DETECT_BIT 0x00001000 + /* PCI/PCI Express outbound window reg */ struct pci_outbound_window_regs { __be32 potar; /* 0x.0 - Outbound translation address register */