From patchwork Thu Jan 9 01:32:43 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Scott Wood X-Patchwork-Id: 308489 X-Patchwork-Delegate: scottwood@freescale.com Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from ozlabs.org (localhost [IPv6:::1]) by ozlabs.org (Postfix) with ESMTP id B186F2C0634 for ; Thu, 9 Jan 2014 12:34:52 +1100 (EST) Received: from na01-bn1-obe.outbound.protection.outlook.com (mail-bn1lp0153.outbound.protection.outlook.com [207.46.163.153]) (using TLSv1 with cipher AES128-SHA (128/128 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 946442C0212 for ; Thu, 9 Jan 2014 12:33:02 +1100 (EST) Received: from snotra.am.freescale.net (192.88.168.50) by BY2PR03MB396.namprd03.prod.outlook.com (10.141.141.26) with Microsoft SMTP Server (TLS) id 15.0.847.13; Thu, 9 Jan 2014 01:32:55 +0000 From: Scott Wood To: Subject: [PATCH v4 3/3] powerpc/fsl-book3e-64: Use paca for hugetlb TLB1 entry selection Date: Wed, 8 Jan 2014 19:32:43 -0600 Message-ID: <1389231163-11175-3-git-send-email-scottwood@freescale.com> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1389231163-11175-1-git-send-email-scottwood@freescale.com> References: <1389231163-11175-1-git-send-email-scottwood@freescale.com> MIME-Version: 1.0 X-Originating-IP: [192.88.168.50] X-ClientProxiedBy: BL2PR08CA001.namprd08.prod.outlook.com (10.255.226.11) To BY2PR03MB396.namprd03.prod.outlook.com (10.141.141.26) X-Forefront-PRVS: 008663486A X-Forefront-Antispam-Report: SFV:NSPM; SFS:(10009001)(199002)(189002)(74366001)(46102001)(51856001)(48376002)(65816001)(80022001)(87976001)(77096001)(66066001)(77156001)(33646001)(85306002)(77982001)(59766001)(47976001)(50986001)(4396001)(50226001)(47736001)(54316002)(49866001)(79102001)(53806001)(42186004)(87266001)(87286001)(56776001)(63696002)(47776003)(76482001)(31966008)(74662001)(69226001)(76796001)(88136002)(81342001)(81686001)(74502001)(47446002)(85852003)(19580395003)(80976001)(83072002)(83322001)(19580405001)(74706001)(50466002)(89996001)(74876001)(36756003)(76786001)(81542001)(81816001)(92566001)(56816005)(90146001)(62966002); DIR:OUT; SFP:1101; SCL:1; SRVR:BY2PR03MB396; H:snotra.am.freescale.net; CLIP:192.88.168.50; FPR:; RD:InfoNoRecords; A:1; MX:1; LANG:en; X-OriginatorOrg: freescale.com Cc: Scott Wood X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.16 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" This keeps usage coordinated for hugetlb and indirect entries, which should make entry selection more predictable and probably improve overall performance when mixing the two. Signed-off-by: Scott Wood --- v4: no change arch/powerpc/mm/hugetlbpage-book3e.c | 51 +++++++++++++++++++++++++++++------- 1 file changed, 41 insertions(+), 10 deletions(-) diff --git a/arch/powerpc/mm/hugetlbpage-book3e.c b/arch/powerpc/mm/hugetlbpage-book3e.c index 646c4bf..5e4ee25 100644 --- a/arch/powerpc/mm/hugetlbpage-book3e.c +++ b/arch/powerpc/mm/hugetlbpage-book3e.c @@ -8,6 +8,44 @@ #include #include +#ifdef CONFIG_PPC_FSL_BOOK3E +#ifdef CONFIG_PPC64 +static inline int tlb1_next(void) +{ + struct paca_struct *paca = get_paca(); + struct tlb_core_data *tcd; + int this, next; + + tcd = paca->tcd_ptr; + this = tcd->esel_next; + + next = this + 1; + if (next >= tcd->esel_max) + next = tcd->esel_first; + + tcd->esel_next = next; + return this; +} +#else +static inline int tlb1_next(void) +{ + int index, ncams; + + ncams = mfspr(SPRN_TLB1CFG) & TLBnCFG_N_ENTRY; + + index = __get_cpu_var(next_tlbcam_idx); + + /* Just round-robin the entries and wrap when we hit the end */ + if (unlikely(index == ncams - 1)) + __get_cpu_var(next_tlbcam_idx) = tlbcam_index; + else + __get_cpu_var(next_tlbcam_idx)++; + + return index; +} +#endif /* !PPC64 */ +#endif /* FSL */ + static inline int mmu_get_tsize(int psize) { return mmu_psize_defs[psize].enc; @@ -47,7 +85,7 @@ void book3e_hugetlb_preload(struct vm_area_struct *vma, unsigned long ea, struct mm_struct *mm; #ifdef CONFIG_PPC_FSL_BOOK3E - int index, ncams; + int index; #endif if (unlikely(is_kernel_addr(ea))) @@ -77,18 +115,11 @@ void book3e_hugetlb_preload(struct vm_area_struct *vma, unsigned long ea, } #ifdef CONFIG_PPC_FSL_BOOK3E - ncams = mfspr(SPRN_TLB1CFG) & TLBnCFG_N_ENTRY; - /* We have to use the CAM(TLB1) on FSL parts for hugepages */ - index = __get_cpu_var(next_tlbcam_idx); + index = tlb1_next(); mtspr(SPRN_MAS0, MAS0_ESEL(index) | MAS0_TLBSEL(1)); - - /* Just round-robin the entries and wrap when we hit the end */ - if (unlikely(index == ncams - 1)) - __get_cpu_var(next_tlbcam_idx) = tlbcam_index; - else - __get_cpu_var(next_tlbcam_idx)++; #endif + mas1 = MAS1_VALID | MAS1_TID(mm->context.id) | MAS1_TSIZE(tsize); mas2 = ea & ~((1UL << shift) - 1); mas2 |= (pte_val(pte) >> PTE_WIMGE_SHIFT) & MAS2_WIMGE_MASK;