From patchwork Tue Jan 7 05:38:06 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dongsheng Wang X-Patchwork-Id: 307537 Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from ozlabs.org (localhost [IPv6:::1]) by ozlabs.org (Postfix) with ESMTP id 6790A2C0130 for ; Tue, 7 Jan 2014 16:41:45 +1100 (EST) Received: from db9outboundpool.messaging.microsoft.com (mail-db9lp0251.outbound.messaging.microsoft.com [213.199.154.251]) (using TLSv1 with cipher AES128-SHA (128/128 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id BCD752C00B7 for ; Tue, 7 Jan 2014 16:41:22 +1100 (EST) Received: from mail131-db9-R.bigfish.com (10.174.16.232) by DB9EHSOBE024.bigfish.com (10.174.14.87) with Microsoft SMTP Server id 14.1.225.22; Tue, 7 Jan 2014 05:41:13 +0000 Received: from mail131-db9 (localhost [127.0.0.1]) by mail131-db9-R.bigfish.com (Postfix) with ESMTP id D00B71E02BA; Tue, 7 Jan 2014 05:41:13 +0000 (UTC) X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPV:NLI; H:mail.freescale.net; RD:none; EFVD:NLI X-SpamScore: 4 X-BigFish: VS4(z37d4lzzz1f42h2148h208ch1ee6h1de0h1fdah2073h2146h1202h1e76h2189h1d1ah1d2ah1fc6hzz1de098h8275bh1de097hz2dh2a8h839hd24he5bhf0ah1288h12a5h12a9h12bdh12e5h137ah139eh13b6h1441h1504h1537h162dh1631h1758h1898h18e1h1946h19b5h1ad9h1b0ah1b2fh2222h224fh1fb3h1d0ch1d2eh1d3fh1dc1h1dfeh1dffh1e23h1fe8h1ff5h2218h2216h226dh22d0h2327h2336h1155h) Received: from mail131-db9 (localhost.localdomain [127.0.0.1]) by mail131-db9 (MessageSwitch) id 1389073272220396_18361; Tue, 7 Jan 2014 05:41:12 +0000 (UTC) Received: from DB9EHSMHS032.bigfish.com (unknown [10.174.16.230]) by mail131-db9.bigfish.com (Postfix) with ESMTP id 2C5611C0049; Tue, 7 Jan 2014 05:41:12 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by DB9EHSMHS032.bigfish.com (10.174.14.42) with Microsoft SMTP Server (TLS) id 14.16.227.3; Tue, 7 Jan 2014 05:41:08 +0000 Received: from tx30smr01.am.freescale.net (10.81.153.31) by 039-SN1MMR1-001.039d.mgd.msft.net (10.84.1.13) with Microsoft SMTP Server (TLS) id 14.3.158.2; Tue, 7 Jan 2014 05:41:07 +0000 Received: from titan.ap.freescale.net (titan.ap.freescale.net [10.192.208.233]) by tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id s075f2tx028245; Mon, 6 Jan 2014 22:41:03 -0700 From: Dongsheng Wang To: , Subject: [PATCH] powerpc/mpic: supply a .disable callback Date: Tue, 7 Jan 2014 13:38:06 +0800 Message-ID: <1389073086-6763-1-git-send-email-dongsheng.wang@freescale.com> X-Mailer: git-send-email 1.8.5 MIME-Version: 1.0 X-OriginatorOrg: freescale.com X-FOPE-CONNECTOR: Id%0$Dn%*$RO%0$TLS%0$FQDN%$TlsDn% X-FOPE-CONNECTOR: Id%0$Dn%FREESCALE.MAIL.ONMICROSOFT.COM$RO%1$TLS%0$FQDN%$TlsDn% Cc: linuxppc-dev@lists.ozlabs.org, Wang Dongsheng X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.16 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" From: Wang Dongsheng Currently MPIC provides .mask, but not .disable. This means that effectively disable_irq() soft-disables the interrupt, and you get a .mask call if an interrupt actually occurs. I'm not sure if this was intended as a performance benefit (it seems common to omit .disable on powerpc interrupt controllers, but nowhere else), but it interacts badly with threaded/workqueue interrupts (including KVM reflection). In such cases, where the real interrupt handler does a disable_irq_nosync(), schedules defered handling, and returns, we get two interrupts for every real interrupt. The second interrupt does nothing but see that IRQ_DISABLED is set, and decide that it would be a good idea to actually call .mask. Signed-off-by: Scott Wood Signed-off-by: Wang Dongsheng diff --git a/arch/powerpc/sysdev/mpic.c b/arch/powerpc/sysdev/mpic.c index 0e166ed..dd7564b 100644 --- a/arch/powerpc/sysdev/mpic.c +++ b/arch/powerpc/sysdev/mpic.c @@ -975,6 +975,7 @@ void mpic_set_destination(unsigned int virq, unsigned int cpuid) } static struct irq_chip mpic_irq_chip = { + .irq_disable = mpic_mask_irq, .irq_mask = mpic_mask_irq, .irq_unmask = mpic_unmask_irq, .irq_eoi = mpic_end_irq, @@ -984,6 +985,7 @@ static struct irq_chip mpic_irq_chip = { #ifdef CONFIG_SMP static struct irq_chip mpic_ipi_chip = { + .irq_disable = mpic_mask_ipi, .irq_mask = mpic_mask_ipi, .irq_unmask = mpic_unmask_ipi, .irq_eoi = mpic_end_ipi, @@ -991,6 +993,7 @@ static struct irq_chip mpic_ipi_chip = { #endif /* CONFIG_SMP */ static struct irq_chip mpic_tm_chip = { + .irq_disable = mpic_mask_tm, .irq_mask = mpic_mask_tm, .irq_unmask = mpic_unmask_tm, .irq_eoi = mpic_end_irq, @@ -1001,6 +1004,7 @@ static struct irq_chip mpic_tm_chip = { static struct irq_chip mpic_irq_ht_chip = { .irq_startup = mpic_startup_ht_irq, .irq_shutdown = mpic_shutdown_ht_irq, + .irq_disable = mpic_mask_irq, .irq_mask = mpic_mask_irq, .irq_unmask = mpic_unmask_ht_irq, .irq_eoi = mpic_end_ht_irq,