From patchwork Mon May 13 21:27:08 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: York Sun X-Patchwork-Id: 243540 Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from ozlabs.org (localhost [IPv6:::1]) by ozlabs.org (Postfix) with ESMTP id 304D02C00C4 for ; Tue, 14 May 2013 07:28:21 +1000 (EST) Received: from tx2outboundpool.messaging.microsoft.com (tx2ehsobe003.messaging.microsoft.com [65.55.88.13]) (using TLSv1 with cipher AES128-SHA (128/128 bits)) (Client CN "mail.global.frontbridge.com", Issuer "MSIT Machine Auth CA 2" (not verified)) by ozlabs.org (Postfix) with ESMTPS id 0466A2C026D for ; Tue, 14 May 2013 07:27:18 +1000 (EST) Received: from mail211-tx2-R.bigfish.com (10.9.14.251) by TX2EHSOBE014.bigfish.com (10.9.40.34) with Microsoft SMTP Server id 14.1.225.23; Mon, 13 May 2013 21:27:14 +0000 Received: from mail211-tx2 (localhost [127.0.0.1]) by mail211-tx2-R.bigfish.com (Postfix) with ESMTP id AB4F4403A0; Mon, 13 May 2013 21:27:14 +0000 (UTC) X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPV:NLI; H:mail.freescale.net; RD:none; EFVD:NLI X-SpamScore: 0 X-BigFish: VS0(zzzz1f42h1ee6h1de0h1fdah1202h1e76h1d1ah1d2ah1fc6hzz8275bhz2dh2a8h668h839hd24he5bhf0ah1288h12a5h12a9h12bdh12e5h137ah139eh13b6h1441h1504h1537h162dh1631h1758h1898h18e1h1946h19b5h1ad9h1b0ah1d0ch1d2eh1d3fh1155h) Received: from mail211-tx2 (localhost.localdomain [127.0.0.1]) by mail211-tx2 (MessageSwitch) id 1368480431226452_489; Mon, 13 May 2013 21:27:11 +0000 (UTC) Received: from TX2EHSMHS013.bigfish.com (unknown [10.9.14.244]) by mail211-tx2.bigfish.com (Postfix) with ESMTP id 33F0744010C; Mon, 13 May 2013 21:27:11 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by TX2EHSMHS013.bigfish.com (10.9.99.113) with Microsoft SMTP Server (TLS) id 14.1.225.23; Mon, 13 May 2013 21:27:10 +0000 Received: from tx30smr01.am.freescale.net (10.81.153.31) by 039-SN1MMR1-001.039d.mgd.msft.net (10.84.1.13) with Microsoft SMTP Server (TLS) id 14.2.328.11; Mon, 13 May 2013 21:27:10 +0000 Received: from oslab-l1.am.freescale.net ([10.214.86.223]) by tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id r4DLR7vW008609; Mon, 13 May 2013 14:27:08 -0700 From: York Sun To: Subject: [PATCH RFC] power/mpc85xx: Add delay after enabling I2C master Date: Mon, 13 May 2013 14:27:08 -0700 Message-ID: <1368480428-23926-1-git-send-email-yorksun@freescale.com> X-Mailer: git-send-email 1.7.9.5 MIME-Version: 1.0 X-OriginatorOrg: freescale.com Cc: linuxppc-dev@lists.ozlabs.org X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" Erratum A-006037 indicates I2C controller executes the write to I2CCR only after it sees SCL idle for 64K cycle of internal I2C controller clocks. If during this waiting period, I2C controller is disabled (I2CCR[MEN] set to 0), then the controller could end in bad state, and hang the future access to I2C register. The mpc_i2c_fixup() function tries to recover the bus from a stalled state where the 9th clock pulse wasn't generated. However, this workaround disables and enables I2C controller without meeting waiting requirement of this erratum. This erratum applies to some 85xx SoCs. It is safe to apply to all of them for mpc_i2c_fixup(). Signed-off-by: York Sun --- I'd like to get rid of the #ifdef if mpc5121 is OK with the longer delay. drivers/i2c/busses/i2c-mpc.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/i2c/busses/i2c-mpc.c b/drivers/i2c/busses/i2c-mpc.c index a69459e..3e540ca 100644 --- a/drivers/i2c/busses/i2c-mpc.c +++ b/drivers/i2c/busses/i2c-mpc.c @@ -105,7 +105,12 @@ static irqreturn_t mpc_i2c_isr(int irq, void *dev_id) static void mpc_i2c_fixup(struct mpc_i2c *i2c) { int k; - u32 delay_val = 1000000 / i2c->real_clk + 1; + u32 delay_val; +#ifdef CONFIG_PPC_85xx + delay_val = 65536 / (fsl_get_sys_freq() / 2000000); /* 64K cycle */ +#else + delay_val = 1000000 / i2c->real_clk + 1; +#endif if (delay_val < 2) delay_val = 2; @@ -115,7 +120,11 @@ static void mpc_i2c_fixup(struct mpc_i2c *i2c) writeccr(i2c, CCR_MSTA | CCR_MTX | CCR_MEN); udelay(delay_val); writeccr(i2c, CCR_MEN); +#ifdef CONFIG_PPC_85xx + udelay(delay_val); +#else udelay(delay_val << 1); +#endif } }