From patchwork Sat May 11 23:26:24 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kevin Hao X-Patchwork-Id: 243159 X-Patchwork-Delegate: scottwood@freescale.com Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from ozlabs.org (localhost [IPv6:::1]) by ozlabs.org (Postfix) with ESMTP id 2740E2C04A2 for ; Sun, 12 May 2013 09:29:17 +1000 (EST) Received: from mail1.windriver.com (mail1.windriver.com [147.11.146.13]) (using TLSv1 with cipher ECDHE-RSA-AES256-SHA (256/256 bits)) (Client CN "mail1.windriver.com", Issuer "Intel External Basic Issuing CA 3A" (not verified)) by ozlabs.org (Postfix) with ESMTPS id 5CE722C0110 for ; Sun, 12 May 2013 09:26:41 +1000 (EST) Received: from ALA-HCA.corp.ad.wrs.com (ala-hca.corp.ad.wrs.com [147.11.189.40]) by mail1.windriver.com (8.14.5/8.14.3) with ESMTP id r4BNQYrF024606 (version=TLSv1/SSLv3 cipher=AES128-SHA bits=128 verify=FAIL); Sat, 11 May 2013 16:26:34 -0700 (PDT) Received: from pek-khao-d1.corp.ad.wrs.com (128.224.162.196) by ALA-HCA.corp.ad.wrs.com (147.11.189.50) with Microsoft SMTP Server id 14.2.342.3; Sat, 11 May 2013 16:26:35 -0700 From: Kevin Hao To: Kumar Gala , Benjamin Herrenschmidt Subject: [PATCH 4/4] powerpc/fsl-book3e: enable the external_input_edge exception handler Date: Sun, 12 May 2013 07:26:24 +0800 Message-ID: <1368314784-971-5-git-send-email-haokexin@gmail.com> X-Mailer: git-send-email 1.8.1.4 In-Reply-To: <1368314784-971-1-git-send-email-haokexin@gmail.com> References: <1368314784-971-1-git-send-email-haokexin@gmail.com> MIME-Version: 1.0 Cc: Scott Wood , linuxppc X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" Enable the external_input_edge exception handler for the fsl ppc64 board when external proxy is enabled. This will leave the irq still hard enabled when a interrupt occurs with irq soft disabled. Signed-off-by: Kevin Hao --- arch/powerpc/platforms/85xx/corenet_ds.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/arch/powerpc/platforms/85xx/corenet_ds.c b/arch/powerpc/platforms/85xx/corenet_ds.c index c59c617..ad688bf 100644 --- a/arch/powerpc/platforms/85xx/corenet_ds.c +++ b/arch/powerpc/platforms/85xx/corenet_ds.c @@ -25,6 +25,9 @@ #include #include #include +#ifdef CONFIG_PPC64 +#include +#endif #include #include @@ -37,8 +40,12 @@ void __init corenet_ds_pic_init(void) unsigned int flags = MPIC_BIG_ENDIAN | MPIC_SINGLE_DEST_CPU | MPIC_NO_RESET; - if (ppc_md.get_irq == mpic_get_coreint_irq) + if (ppc_md.get_irq == mpic_get_coreint_irq) { flags |= MPIC_ENABLE_COREINT; +#ifdef CONFIG_PPC64 + patch_exception(0x0a0, exc_external_input_edge_book3e); +#endif + } mpic = mpic_alloc(NULL, 0, flags, 0, 512, " OpenPIC "); BUG_ON(mpic == NULL);