From patchwork Fri Mar 15 07:26:30 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gavin Shan X-Patchwork-Id: 227862 Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from ozlabs.org (localhost [IPv6:::1]) by ozlabs.org (Postfix) with ESMTP id 4D51C2C0236 for ; Fri, 15 Mar 2013 18:28:23 +1100 (EST) Received: from e37.co.us.ibm.com (e37.co.us.ibm.com [32.97.110.158]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "e37.co.us.ibm.com", Issuer "GeoTrust SSL CA" (not verified)) by ozlabs.org (Postfix) with ESMTPS id 647C42C00DF for ; Fri, 15 Mar 2013 18:26:43 +1100 (EST) Received: from /spool/local by e37.co.us.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Fri, 15 Mar 2013 01:26:42 -0600 Received: from d03dlp01.boulder.ibm.com (9.17.202.177) by e37.co.us.ibm.com (192.168.1.137) with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted; Fri, 15 Mar 2013 01:26:40 -0600 Received: from d03relay03.boulder.ibm.com (d03relay03.boulder.ibm.com [9.17.195.228]) by d03dlp01.boulder.ibm.com (Postfix) with ESMTP id 18CF61FF0039 for ; Fri, 15 Mar 2013 01:21:45 -0600 (MDT) Received: from d03av02.boulder.ibm.com (d03av02.boulder.ibm.com [9.17.195.168]) by d03relay03.boulder.ibm.com (8.13.8/8.13.8/NCO v10.0) with ESMTP id r2F7QdUL086788 for ; Fri, 15 Mar 2013 01:26:39 -0600 Received: from d03av02.boulder.ibm.com (loopback [127.0.0.1]) by d03av02.boulder.ibm.com (8.14.4/8.13.1/NCO v10.0 AVout) with ESMTP id r2F7QbAX014464 for ; Fri, 15 Mar 2013 01:26:39 -0600 Received: from shangw ([9.77.179.176]) by d03av02.boulder.ibm.com (8.14.4/8.13.1/NCO v10.0 AVin) with ESMTP id r2F7QZNX014373; Fri, 15 Mar 2013 01:26:36 -0600 Received: by shangw (Postfix, from userid 1000) id B66333021F9; Fri, 15 Mar 2013 15:26:33 +0800 (CST) From: Gavin Shan To: kvm@vger.kernel.org, linuxppc-dev@lists.ozlabs.org Subject: [PATCH 3/3] VFIO: Direct access config reg without capability Date: Fri, 15 Mar 2013 15:26:30 +0800 Message-Id: <1363332390-12754-4-git-send-email-shangw@linux.vnet.ibm.com> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1363332390-12754-1-git-send-email-shangw@linux.vnet.ibm.com> References: <1363332390-12754-1-git-send-email-shangw@linux.vnet.ibm.com> X-TM-AS-MML: No X-Content-Scanned: Fidelis XPS MAILER x-cbid: 13031507-7408-0000-0000-00000DD43A56 Cc: aik@ozlabs.ru, alex.williamson@redhat.com, Gavin Shan X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" The config registers in [0, 0x40] is being supported by VFIO. Apart from that, the other config registers should be coverred by PCI or PCIe capability. However, there might have some PCI devices (be2net) who has config registers (0x7c) out of [0, 0x40], and don't have corresponding PCI or PCIe capability. VFIO will return 0x0 on reading those registers and writing is dropped. It caused the be2net driver fails to be loaded because 0x0 returned from its config register 0x7c. The patch changes the behaviour so that those config registers out of [0, 0x40] and don't have corresponding PCI or PCIe capability will be accessed directly. Signed-off-by: Gavin Shan --- drivers/vfio/pci/vfio_pci_config.c | 31 ++++++++++++++++++++----------- 1 files changed, 20 insertions(+), 11 deletions(-) diff --git a/drivers/vfio/pci/vfio_pci_config.c b/drivers/vfio/pci/vfio_pci_config.c index 964ff22..5ea3afb 100644 --- a/drivers/vfio/pci/vfio_pci_config.c +++ b/drivers/vfio/pci/vfio_pci_config.c @@ -1471,18 +1471,27 @@ static ssize_t vfio_config_do_rw(struct vfio_pci_device *vdev, char __user *buf, cap_id = vdev->pci_config_map[*ppos / 4]; + /* + * Some PCI device config registers might not be coverred by + * capability and useful. We will enable direct access to + * those registers. + */ if (cap_id == PCI_CAP_ID_INVALID) { - if (iswrite) - return ret; /* drop */ - - /* - * Per PCI spec 3.0, section 6.1, reads from reserved and - * unimplemented registers return 0 - */ - if (copy_to_user(buf, &val, count)) - return -EFAULT; - - return ret; + if (iswrite) { + if (copy_from_user(&val, buf, count)) + return -EFAULT; + ret = vfio_user_config_write(vdev->pdev, (int)(*ppos), + val, count); + return ret ? ret : count; + } else { + ret = vfio_user_config_read(vdev->pdev, (int)(*ppos), + &val, count); + if (ret) + return ret; + if (copy_to_user(buf, &val, count)) + return -EFAULT; + return count; + } } /*