From patchwork Thu Oct 4 11:56:47 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sethi Varun-B16395 X-Patchwork-Id: 189091 Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from ozlabs.org (localhost [IPv6:::1]) by ozlabs.org (Postfix) with ESMTP id 4DD952C0507 for ; Thu, 4 Oct 2012 22:02:17 +1000 (EST) Received: from ch1outboundpool.messaging.microsoft.com (ch1ehsobe004.messaging.microsoft.com [216.32.181.184]) (using TLSv1 with cipher AES128-SHA (128/128 bits)) (Client CN "mail.global.frontbridge.com", Issuer "Microsoft Secure Server Authority" (not verified)) by ozlabs.org (Postfix) with ESMTPS id AA8232C0371 for ; Thu, 4 Oct 2012 22:00:33 +1000 (EST) Received: from mail131-ch1-R.bigfish.com (10.43.68.239) by CH1EHSOBE013.bigfish.com (10.43.70.63) with Microsoft SMTP Server id 14.1.225.23; Thu, 4 Oct 2012 12:00:27 +0000 Received: from mail131-ch1 (localhost [127.0.0.1]) by mail131-ch1-R.bigfish.com (Postfix) with ESMTP id 827054007C for ; Thu, 4 Oct 2012 12:00:27 +0000 (UTC) X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPV:NLI; H:mail.freescale.net; RD:none; EFVD:NLI X-SpamScore: 0 X-BigFish: VS0(zzd799hzz1202h1d1ah1d2ahzz8275bhz2dh2a8h668h839hd24he5bhf0ah1288h12a5h12a9h12bdh12e5h137ah139eh13b6h1441h1155h) Received: from mail131-ch1 (localhost.localdomain [127.0.0.1]) by mail131-ch1 (MessageSwitch) id 1349352025131809_19459; Thu, 4 Oct 2012 12:00:25 +0000 (UTC) Received: from CH1EHSMHS016.bigfish.com (snatpool1.int.messaging.microsoft.com [10.43.68.244]) by mail131-ch1.bigfish.com (Postfix) with ESMTP id 1D0982600AA for ; Thu, 4 Oct 2012 12:00:25 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by CH1EHSMHS016.bigfish.com (10.43.70.16) with Microsoft SMTP Server (TLS) id 14.1.225.23; Thu, 4 Oct 2012 12:00:22 +0000 Received: from tx30smr01.am.freescale.net (10.81.153.31) by 039-SN1MMR1-003.039d.mgd.msft.net (10.84.1.16) with Microsoft SMTP Server (TLS) id 14.2.309.3; Thu, 4 Oct 2012 07:00:22 -0500 Received: from nmglablinux27.zin33.ap.freescale.net ([10.213.130.145]) by tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id q94C0KwP019833 for ; Thu, 4 Oct 2012 05:00:21 -0700 Received: from nmglablinux27.zin33.ap.freescale.net (localhost [127.0.0.1]) by nmglablinux27.zin33.ap.freescale.net (8.14.4/8.14.4/Debian-2ubuntu1) with ESMTP id q94Bux77007226; Thu, 4 Oct 2012 17:26:59 +0530 Received: (from varuns@localhost) by nmglablinux27.zin33.ap.freescale.net (8.14.4/8.14.4/Submit) id q94Buxoi007224; Thu, 4 Oct 2012 17:26:59 +0530 From: To: , , , Subject: [PATCH 2/3 v2] iommu/fsl: Add iommu domain attributes required by fsl PAMU driver. Date: Thu, 4 Oct 2012 17:26:47 +0530 Message-ID: <1349351808-7156-3-git-send-email-b16395@freescale.com> X-Mailer: git-send-email 1.7.4.1 In-Reply-To: <1349351808-7156-1-git-send-email-b16395@freescale.com> References: <1349351808-7156-1-git-send-email-b16395@freescale.com> MIME-Version: 1.0 X-OriginatorOrg: freescale.net Cc: Varun Sethi X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" From: Varun Sethi Added the following domain attributes required by FSL PAMU driver: 1. Subwindows field added to the iommu domain geometry attribute. 2. Added new iommu stash attribute, which allows setting of the LIODN specific stash id parameter through IOMMU API. 3. Added an attribute for enabling/disabling DMA to a particular memory window. Signed-off-by: Varun Sethi --- include/linux/iommu.h | 35 +++++++++++++++++++++++++++++++++++ 1 files changed, 35 insertions(+), 0 deletions(-) diff --git a/include/linux/iommu.h b/include/linux/iommu.h index f3b99e1..62e22f0 100644 --- a/include/linux/iommu.h +++ b/include/linux/iommu.h @@ -44,6 +44,33 @@ struct iommu_domain_geometry { dma_addr_t aperture_start; /* First address that can be mapped */ dma_addr_t aperture_end; /* Last address that can be mapped */ bool force_aperture; /* DMA only allowed in mappable range? */ + + /* The subwindows field indicates number of DMA subwindows supported + * by the geometry. Following is the interpretation of + * values for this field: + * 0 : This implies that the supported geometry size is 1 MB + * with each subwindow size being 4KB. Thus number of subwindows + * being = 1MB/4KB = 256. + * 1 : Only one DMA window i.e. no subwindows. + * value other than 0 or 1 would indicate actual number of subwindows. + */ + u32 subwindows; +}; + +/* cache stash targets */ +#define L1_CACHE 1 +#define L2_CACHE 2 +#define L3_CACHE 3 + +/* This attribute corresponds to IOMMUs capable of generating + * a stash transaction. A stash transaction is typically a + * hardware initiated prefetch of data from memory to cache. + * This attribute allows configuring stashig specific parameters + * in the IOMMU hardware. + */ +struct iommu_stash_attribute { + u32 cpu; /* cpu number */ + u32 cache; /* cache to stash to: L1,L2,L3 */ }; struct iommu_domain { @@ -60,6 +87,14 @@ struct iommu_domain { enum iommu_attr { DOMAIN_ATTR_MAX, DOMAIN_ATTR_GEOMETRY, + /* Set the IOMMU hardware stashing + * parameters. + */ + DOMAIN_ATTR_STASH, + /* Explicity enable/disable DMA for a + * particular memory window. + */ + DOMAIN_ATTR_ENABLE, }; #ifdef CONFIG_IOMMU_API