From patchwork Mon Sep 24 14:01:35 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shengzhou Liu X-Patchwork-Id: 186443 Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from ozlabs.org (localhost [IPv6:::1]) by ozlabs.org (Postfix) with ESMTP id 8BC8D2C0178 for ; Tue, 25 Sep 2012 00:38:25 +1000 (EST) Received: from am1outboundpool.messaging.microsoft.com (am1ehsobe004.messaging.microsoft.com [213.199.154.207]) (using TLSv1 with cipher AES128-SHA (128/128 bits)) (Client CN "mail.global.frontbridge.com", Issuer "Microsoft Secure Server Authority" (not verified)) by ozlabs.org (Postfix) with ESMTPS id ADCAB2C0085 for ; Tue, 25 Sep 2012 00:37:57 +1000 (EST) Received: from mail71-am1-R.bigfish.com (10.3.201.245) by AM1EHSOBE008.bigfish.com (10.3.204.28) with Microsoft SMTP Server id 14.1.225.23; Mon, 24 Sep 2012 14:37:50 +0000 Received: from mail71-am1 (localhost [127.0.0.1]) by mail71-am1-R.bigfish.com (Postfix) with ESMTP id E4B214E005C; Mon, 24 Sep 2012 14:37:50 +0000 (UTC) X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPV:NLI; H:mail.freescale.net; RD:none; EFVD:NLI X-SpamScore: 1 X-BigFish: VS1(zzd6f1izz1202h1d1ah1d2ahzz8275bhz2dh2a8h668h839he5bhf0ah107ah1288h12a5h12a9h12bdh12e5h1354h137ah139eh1155h) Received: from mail71-am1 (localhost.localdomain [127.0.0.1]) by mail71-am1 (MessageSwitch) id 1348497469111364_11305; Mon, 24 Sep 2012 14:37:49 +0000 (UTC) Received: from AM1EHSMHS009.bigfish.com (unknown [10.3.201.247]) by mail71-am1.bigfish.com (Postfix) with ESMTP id 18E54120119; Mon, 24 Sep 2012 14:37:49 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by AM1EHSMHS009.bigfish.com (10.3.207.109) with Microsoft SMTP Server (TLS) id 14.1.225.23; Mon, 24 Sep 2012 14:37:46 +0000 Received: from az84smr01.freescale.net (10.64.34.197) by 039-SN1MMR1-002.039d.mgd.msft.net (10.84.1.15) with Microsoft SMTP Server (TLS) id 14.2.309.3; Mon, 24 Sep 2012 09:37:15 -0500 Received: from localhost.localdomain (rock.ap.freescale.net [10.193.20.106]) by az84smr01.freescale.net (8.14.3/8.14.0) with ESMTP id q8OEb8tf007409; Mon, 24 Sep 2012 07:37:08 -0700 From: Shengzhou Liu To: , Subject: [PATCH] powerpc/usb: remove checking PHY_CLK_VALID for UTMI PHY Date: Mon, 24 Sep 2012 22:01:35 +0800 Message-ID: <1348495295-19109-1-git-send-email-Shengzhou.Liu@freescale.com> X-Mailer: git-send-email 1.6.4 MIME-Version: 1.0 X-OriginatorOrg: freescale.com Cc: linux-usb@vger.kernel.org, Shengzhou Liu X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" PHY_CLK_VALID bit doesn't work properly with UTMI PHY. e.g. This bit is always zero on P5040, etc. There is no need to check this bit for UTMI PHY, just keep checking for ULPI PHY to prevent system hanging. This patch should be squashed into previous commit 3735ba8db8e6e "powerpc/usb: fix bug of CPU hang when missing USB PHY clock" Signed-off-by: Shengzhou Liu --- drivers/usb/host/ehci-fsl.c | 3 +-- include/linux/fsl_devices.h | 2 +- 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c index 11ff4b4..9bfde82 100644 --- a/drivers/usb/host/ehci-fsl.c +++ b/drivers/usb/host/ehci-fsl.c @@ -267,8 +267,7 @@ static int ehci_fsl_setup_phy(struct usb_hcd *hcd, break; } - if ((pdata->controller_ver) && ((phy_mode == FSL_USB2_PHY_ULPI) || - (phy_mode == FSL_USB2_PHY_UTMI))) { + if (pdata->controller_ver && (phy_mode == FSL_USB2_PHY_ULPI)) { /* check PHY_CLK_VALID to get phy clk valid */ if (!spin_event_timeout(in_be32(non_ehci + FSL_SOC_USB_CTRL) & PHY_CLK_VALID, FSL_USB_PHY_CLK_TIMEOUT, 0)) { diff --git a/include/linux/fsl_devices.h b/include/linux/fsl_devices.h index ccfc4bb..700bf31 100644 --- a/include/linux/fsl_devices.h +++ b/include/linux/fsl_devices.h @@ -19,7 +19,7 @@ #define FSL_UTMI_PHY_DLY 10 /*As per P1010RM, delay for UTMI PHY CLK to become stable - 10ms*/ -#define FSL_USB_PHY_CLK_TIMEOUT 1000 /* uSec */ +#define FSL_USB_PHY_CLK_TIMEOUT 10000 /* uSec */ #define FSL_USB_VER_OLD 0 #define FSL_USB_VER_1_6 1 #define FSL_USB_VER_2_2 2