From patchwork Thu Jul 26 14:47:55 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Manoil X-Patchwork-Id: 173447 X-Patchwork-Delegate: galak@kernel.crashing.org Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from ozlabs.org (localhost [IPv6:::1]) by ozlabs.org (Postfix) with ESMTP id D025F2C03E8 for ; Fri, 27 Jul 2012 00:49:04 +1000 (EST) Received: from co1outboundpool.messaging.microsoft.com (co1ehsobe002.messaging.microsoft.com [216.32.180.185]) (using TLSv1 with cipher AES128-SHA (128/128 bits)) (Client CN "mail.global.frontbridge.com", Issuer "Microsoft Secure Server Authority" (not verified)) by ozlabs.org (Postfix) with ESMTPS id 43B542C0097 for ; Fri, 27 Jul 2012 00:48:38 +1000 (EST) Received: from mail24-co1-R.bigfish.com (10.243.78.245) by CO1EHSOBE009.bigfish.com (10.243.66.72) with Microsoft SMTP Server id 14.1.225.23; Thu, 26 Jul 2012 14:48:34 +0000 Received: from mail24-co1 (localhost [127.0.0.1]) by mail24-co1-R.bigfish.com (Postfix) with ESMTP id DB8BFCC02FA; Thu, 26 Jul 2012 14:48:33 +0000 (UTC) X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPV:NLI; H:mail.freescale.net; RD:none; EFVD:NLI X-SpamScore: 0 X-BigFish: VS0(zzzz1202hzz8275bhz2dh2a8h668h839hd24he5bhf0ah) Received: from mail24-co1 (localhost.localdomain [127.0.0.1]) by mail24-co1 (MessageSwitch) id 134331411294424_29003; Thu, 26 Jul 2012 14:48:32 +0000 (UTC) Received: from CO1EHSMHS014.bigfish.com (unknown [10.243.78.239]) by mail24-co1.bigfish.com (Postfix) with ESMTP id 13FE9280050; Thu, 26 Jul 2012 14:48:32 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by CO1EHSMHS014.bigfish.com (10.243.66.24) with Microsoft SMTP Server (TLS) id 14.1.225.23; Thu, 26 Jul 2012 14:48:30 +0000 Received: from tx30smr01.am.freescale.net (10.81.153.31) by 039-SN1MMR1-001.039d.mgd.msft.net (10.84.1.13) with Microsoft SMTP Server (TLS) id 14.2.298.5; Thu, 26 Jul 2012 09:48:29 -0500 Received: from zro04cle141.ea.freescale.net (udp157456uds.ea.freescale.net [140.101.223.141]) by tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id q6QEmPno013894; Thu, 26 Jul 2012 07:48:26 -0700 Received: by zro04cle141.ea.freescale.net (Postfix, from userid 23113) id D6E9C4007C; Thu, 26 Jul 2012 17:48:24 +0300 (EEST) From: Claudiu Manoil To: Subject: [PATCH][v1] powerpc/85xx: Fix sram_offset parameter type Date: Thu, 26 Jul 2012 17:47:55 +0300 Message-ID: <1343314075-2127-1-git-send-email-claudiu.manoil@freescale.com> X-Mailer: git-send-email 1.6.6 MIME-Version: 1.0 X-OriginatorOrg: freescale.net Cc: Tang Yuantian , Claudiu Manoil X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" The sram_offset parameter represents a physical address and should be of type phys_addr_t. As part of this fix, the extraction of sram_params is being cleaned-up and fixed. This patch fixes now the case when the offset value of 0xfff00000 was being rejected by the driver (returning -EINVAL), although this is a valid offset value. Signed-off-by: Tang Yuantian Signed-off-by: Claudiu Manoil --- v1: fixed copyright year format arch/powerpc/sysdev/fsl_85xx_cache_ctlr.h | 4 +- arch/powerpc/sysdev/fsl_85xx_l2ctlr.c | 39 ++++++++++------------------ 2 files changed, 16 insertions(+), 27 deletions(-) diff --git a/arch/powerpc/sysdev/fsl_85xx_cache_ctlr.h b/arch/powerpc/sysdev/fsl_85xx_cache_ctlr.h index 60c9c0b..2aa97dd 100644 --- a/arch/powerpc/sysdev/fsl_85xx_cache_ctlr.h +++ b/arch/powerpc/sysdev/fsl_85xx_cache_ctlr.h @@ -1,5 +1,5 @@ /* - * Copyright 2009-2010 Freescale Semiconductor, Inc + * Copyright 2009-2010, 2012 Freescale Semiconductor, Inc * * QorIQ based Cache Controller Memory Mapped Registers * @@ -91,7 +91,7 @@ struct mpc85xx_l2ctlr { struct sram_parameters { unsigned int sram_size; - uint64_t sram_offset; + phys_addr_t sram_offset; }; extern int instantiate_cache_sram(struct platform_device *dev, diff --git a/arch/powerpc/sysdev/fsl_85xx_l2ctlr.c b/arch/powerpc/sysdev/fsl_85xx_l2ctlr.c index 611bb4b..d131c8a 100644 --- a/arch/powerpc/sysdev/fsl_85xx_l2ctlr.c +++ b/arch/powerpc/sysdev/fsl_85xx_l2ctlr.c @@ -1,5 +1,5 @@ /* - * Copyright 2009-2010 Freescale Semiconductor, Inc. + * Copyright 2009-2010, 2012 Freescale Semiconductor, Inc. * * QorIQ (P1/P2) L2 controller init for Cache-SRAM instantiation * @@ -31,24 +31,21 @@ static char *sram_size; static char *sram_offset; struct mpc85xx_l2ctlr __iomem *l2ctlr; -static long get_cache_sram_size(void) +static int get_cache_sram_params(struct sram_parameters *sram_params) { - unsigned long val; + unsigned long long addr; + unsigned int size; - if (!sram_size || (strict_strtoul(sram_size, 0, &val) < 0)) + if (!sram_size || (kstrtouint(sram_size, 0, &size) < 0)) return -EINVAL; - return val; -} - -static long get_cache_sram_offset(void) -{ - unsigned long val; - - if (!sram_offset || (strict_strtoul(sram_offset, 0, &val) < 0)) + if (!sram_offset || (kstrtoull(sram_offset, 0, &addr) < 0)) return -EINVAL; - return val; + sram_params->sram_offset = addr; + sram_params->sram_size = size; + + return 0; } static int __init get_size_from_cmdline(char *str) @@ -93,17 +90,9 @@ static int __devinit mpc85xx_l2ctlr_of_probe(struct platform_device *dev) } l2cache_size = *prop; - sram_params.sram_size = get_cache_sram_size(); - if ((int)sram_params.sram_size <= 0) { - dev_err(&dev->dev, - "Entire L2 as cache, Aborting Cache-SRAM stuff\n"); - return -EINVAL; - } - - sram_params.sram_offset = get_cache_sram_offset(); - if ((int64_t)sram_params.sram_offset <= 0) { + if (get_cache_sram_params(&sram_params)) { dev_err(&dev->dev, - "Entire L2 as cache, provide a valid sram offset\n"); + "Entire L2 as cache, provide valid sram offset and size\n"); return -EINVAL; } @@ -125,14 +114,14 @@ static int __devinit mpc85xx_l2ctlr_of_probe(struct platform_device *dev) * Write bits[0-17] to srbar0 */ out_be32(&l2ctlr->srbar0, - sram_params.sram_offset & L2SRAM_BAR_MSK_LO18); + lower_32_bits(sram_params.sram_offset) & L2SRAM_BAR_MSK_LO18); /* * Write bits[18-21] to srbare0 */ #ifdef CONFIG_PHYS_64BIT out_be32(&l2ctlr->srbarea0, - (sram_params.sram_offset >> 32) & L2SRAM_BARE_MSK_HI4); + upper_32_bits(sram_params.sram_offset) & L2SRAM_BARE_MSK_HI4); #endif clrsetbits_be32(&l2ctlr->ctl, L2CR_L2E, L2CR_L2FI);