From patchwork Tue Jul 24 10:20:06 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hongtao Jia X-Patchwork-Id: 172823 X-Patchwork-Delegate: galak@kernel.crashing.org Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from ozlabs.org (localhost [IPv6:::1]) by ozlabs.org (Postfix) with ESMTP id 86BA92C0338 for ; Tue, 24 Jul 2012 20:44:41 +1000 (EST) Received: from va3outboundpool.messaging.microsoft.com (va3ehsobe003.messaging.microsoft.com [216.32.180.13]) (using TLSv1 with cipher AES128-SHA (128/128 bits)) (Client CN "mail.global.frontbridge.com", Issuer "Microsoft Secure Server Authority" (not verified)) by ozlabs.org (Postfix) with ESMTPS id 6BA0B2C008D for ; Tue, 24 Jul 2012 20:43:28 +1000 (EST) Received: from mail138-va3-R.bigfish.com (10.7.14.254) by VA3EHSOBE007.bigfish.com (10.7.40.11) with Microsoft SMTP Server id 14.1.225.23; Tue, 24 Jul 2012 10:43:24 +0000 Received: from mail138-va3 (localhost [127.0.0.1]) by mail138-va3-R.bigfish.com (Postfix) with ESMTP id 77A70220288; Tue, 24 Jul 2012 10:43:24 +0000 (UTC) X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPV:NLI; H:mail.freescale.net; RD:none; EFVD:NLI X-SpamScore: 0 X-BigFish: VS0(zzzz1202hzz8275bhz2dh2a8h668h839he5bhf0ah107ah) Received: from mail138-va3 (localhost.localdomain [127.0.0.1]) by mail138-va3 (MessageSwitch) id 134312660350465_22365; Tue, 24 Jul 2012 10:43:23 +0000 (UTC) Received: from VA3EHSMHS029.bigfish.com (unknown [10.7.14.238]) by mail138-va3.bigfish.com (Postfix) with ESMTP id F365C1E004C; Tue, 24 Jul 2012 10:43:22 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by VA3EHSMHS029.bigfish.com (10.7.99.39) with Microsoft SMTP Server (TLS) id 14.1.225.23; Tue, 24 Jul 2012 10:43:23 +0000 Received: from az84smr01.freescale.net (10.64.34.197) by 039-SN1MMR1-001.039d.mgd.msft.net (10.84.1.13) with Microsoft SMTP Server (TLS) id 14.2.298.5; Tue, 24 Jul 2012 05:43:22 -0500 Received: from rock.am.freescale.net (rock.ap.freescale.net [10.193.20.106]) by az84smr01.freescale.net (8.14.3/8.14.0) with ESMTP id q6OAhCfY016024; Tue, 24 Jul 2012 03:43:19 -0700 From: Jia Hongtao To: , , Subject: [PATCH 2/6] powerpc/fsl-pci: Check swiotlb enable at board setup_arch stage Date: Tue, 24 Jul 2012 18:20:06 +0800 Message-ID: <1343125210-16720-2-git-send-email-B38951@freescale.com> X-Mailer: git-send-email 1.7.5.1 In-Reply-To: <1343125210-16720-1-git-send-email-B38951@freescale.com> References: <1343125210-16720-1-git-send-email-B38951@freescale.com> MIME-Version: 1.0 X-OriginatorOrg: freescale.com Cc: b38951@freescale.com X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" PCI initialization is called later than swiotlb_init() due to PCI controller is a platform driver now. So we provide a function which called at board setup_arch stage to address swiotlb enable by parsing pci ranges. Signed-off-by: Jia Hongtao Signed-off-by: Li Yang --- arch/powerpc/sysdev/fsl_pci.c | 125 ++++++++++++++++++++++++++++++++++++----- arch/powerpc/sysdev/fsl_pci.h | 6 ++ 2 files changed, 116 insertions(+), 15 deletions(-) diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c index feed364..99a3e78 100644 --- a/arch/powerpc/sysdev/fsl_pci.c +++ b/arch/powerpc/sysdev/fsl_pci.c @@ -822,6 +822,116 @@ static const struct of_device_id pci_ids[] = { {}, }; +#ifdef CONFIG_SWIOTLB +void pci_check_swiotlb(void) +{ + const u32 *ranges; + int rlen; + int pna; + int np; + struct device_node *node; + int memno; + u32 pci_space; + unsigned long long pci_addr, cpu_addr, pci_next, cpu_next, size; + unsigned long long pci_addr_lo = ULLONG_MAX; + unsigned long long pci_addr_hi = 0x0; + dma_addr_t pci_dma_sz; + + for_each_node_by_type(node, "pci") { + if (of_match_node(pci_ids, node)) { + memno = 0; + pna = of_n_addr_cells(node); + np = pna + 5; + /* Get ranges property */ + ranges = of_get_property(node, "ranges", &rlen); + if (ranges == NULL) + return; + + /* Parse outbound MEM window range */ + while ((rlen -= np * 4) >= 0) { + /* Read next ranges element */ + pci_space = ranges[0]; + if (!((pci_space >> 24) & 0x2)) { + ranges += np; + break; + } + pci_addr = of_read_number(ranges + 1, 2); + cpu_addr = of_translate_address( + node, ranges + 3); + size = of_read_number(ranges + pna + 3, 2); + ranges += np; + + /* + * If we failed translation or got a zero-sized + * region (some FW try to feed us with non + * sensical zero sized regions such as power3 + * which look like some kind of attempt at + * exposing the VGA memory hole) + */ + if (cpu_addr == OF_BAD_ADDR || size == 0) + continue; + + /* + * Now consume following elements while they + * are contiguous + */ + for (; rlen >= np * sizeof(u32); + ranges += np, rlen -= np * 4) { + if (ranges[0] != pci_space) + break; + pci_next = of_read_number(ranges + 1, + 2); + cpu_next = of_translate_address(node, + ranges + 3); + if (pci_next != pci_addr + size || + cpu_next != cpu_addr + size) + break; + size += of_read_number( + ranges + pna + 3, 2); + } + + /* We support only 3 memory ranges */ + if (memno >= 3) { + printk(KERN_INFO + " \\--> Skipped (too many) !\n"); + continue; + } + + pci_addr_lo = min(pci_addr, pci_addr_lo); + pci_addr_hi = max(pci_addr + size, pci_addr_hi); + memno++; + } + } + } + + /* Get PEXCSRBAR size (equal to CCSR size) */ + node = of_find_node_by_type(NULL, "soc"); + ranges = of_get_property(node, "ranges", &rlen); + if (ranges == NULL) + return; + + size = of_read_number(ranges + 3, 1); + of_node_put(node); + + if (pci_addr_hi < (0x100000000ull - size)) + pci_dma_sz = pci_addr_lo; + else + pci_dma_sz = pci_addr_lo - size; + + /* + * if we couldn't map all of DRAM via the dma windows + * we need SWIOTLB to handle buffers located outside of + * dma capable memory region + */ + if (memblock_end_of_DRAM() > pci_dma_sz) { + ppc_swiotlb_enable = 1; + set_pci_dma_ops(&swiotlb_dma_ops); + ppc_md.pci_dma_dev_setup = + pci_dma_dev_setup_swiotlb; + } +} +#endif + int primary_phb_addr; static int __devinit fsl_pci_probe(struct platform_device *pdev) { @@ -833,21 +943,6 @@ static int __devinit fsl_pci_probe(struct platform_device *pdev) of_address_to_resource(pdev->dev.of_node, 0, &rsrc); is_primary = ((rsrc.start & 0xfffff) == primary_phb_addr); fsl_add_bridge(pdev->dev.of_node, is_primary); - -#ifdef CONFIG_SWIOTLB - hose = pci_find_hose_for_OF_device(pdev->dev.of_node); - /* - * if we couldn't map all of DRAM via the dma windows - * we need SWIOTLB to handle buffers located outside of - * dma capable memory region - */ - if (memblock_end_of_DRAM() > hose->dma_window_base_cur - + hose->dma_window_size) { - ppc_swiotlb_enable = 1; - set_pci_dma_ops(&swiotlb_dma_ops); - ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_swiotlb; - } -#endif } return 0; diff --git a/arch/powerpc/sysdev/fsl_pci.h b/arch/powerpc/sysdev/fsl_pci.h index df9fc44..c2c1de5 100644 --- a/arch/powerpc/sysdev/fsl_pci.h +++ b/arch/powerpc/sysdev/fsl_pci.h @@ -94,5 +94,11 @@ extern void fsl_pcibios_fixup_bus(struct pci_bus *bus); extern int mpc83xx_add_bridge(struct device_node *dev); u64 fsl_pci_immrbar_base(struct pci_controller *hose); +#ifdef CONFIG_SWIOTLB +extern void pci_check_swiotlb(void); +#else +static inline void pci_check_swiotlb(void) {} +#endif + #endif /* __POWERPC_FSL_PCI_H */ #endif /* __KERNEL__ */