From patchwork Mon Jul 16 03:35:30 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hongtao Jia X-Patchwork-Id: 171132 X-Patchwork-Delegate: galak@kernel.crashing.org Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from ozlabs.org (localhost [IPv6:::1]) by ozlabs.org (Postfix) with ESMTP id 0AE412C0226 for ; Mon, 16 Jul 2012 13:57:45 +1000 (EST) Received: from am1outboundpool.messaging.microsoft.com (am1ehsobe006.messaging.microsoft.com [213.199.154.209]) (using TLSv1 with cipher AES128-SHA (128/128 bits)) (Client CN "mail.global.frontbridge.com", Issuer "Microsoft Secure Server Authority" (not verified)) by ozlabs.org (Postfix) with ESMTPS id 8A2CB2C00CE for ; Mon, 16 Jul 2012 13:57:15 +1000 (EST) Received: from mail87-am1-R.bigfish.com (10.3.201.234) by AM1EHSOBE008.bigfish.com (10.3.204.28) with Microsoft SMTP Server id 14.1.225.23; Mon, 16 Jul 2012 03:57:09 +0000 Received: from mail87-am1 (localhost [127.0.0.1]) by mail87-am1-R.bigfish.com (Postfix) with ESMTP id A7C651E0402; Mon, 16 Jul 2012 03:57:09 +0000 (UTC) X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPV:NLI; H:mail.freescale.net; RD:none; EFVD:NLI X-SpamScore: 0 X-BigFish: VS0(zzzz1202hzz8275bhz2dh2a8h668h839he5bhf0ah107ah) Received: from mail87-am1 (localhost.localdomain [127.0.0.1]) by mail87-am1 (MessageSwitch) id 13424110286949_8469; Mon, 16 Jul 2012 03:57:08 +0000 (UTC) Received: from AM1EHSMHS007.bigfish.com (unknown [10.3.201.246]) by mail87-am1.bigfish.com (Postfix) with ESMTP id F3BEF3A0045; Mon, 16 Jul 2012 03:57:07 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by AM1EHSMHS007.bigfish.com (10.3.207.107) with Microsoft SMTP Server (TLS) id 14.1.225.23; Mon, 16 Jul 2012 03:57:08 +0000 Received: from az84smr01.freescale.net (10.64.34.197) by 039-SN1MMR1-002.039d.mgd.msft.net (10.84.1.15) with Microsoft SMTP Server (TLS) id 14.2.298.5; Sun, 15 Jul 2012 22:57:05 -0500 Received: from rock.am.freescale.net (rock.ap.freescale.net [10.193.20.106]) by az84smr01.freescale.net (8.14.3/8.14.0) with ESMTP id q6G3v13W008844; Sun, 15 Jul 2012 20:57:02 -0700 From: Jia Hongtao To: , Subject: [PATCH] powerpc/85xx: workaround for chips with MSI hareware errata to support MSI-X Date: Mon, 16 Jul 2012 11:35:30 +0800 Message-ID: <1342409730-28340-1-git-send-email-B38951@freescale.com> X-Mailer: git-send-email 1.7.5.1 MIME-Version: 1.0 X-OriginatorOrg: freescale.com Cc: soniccat.liu@gmail.com, b38951@freescale.com X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" From: Liu Shuo The MPIC chip with version 2.0 has a MSI errata (errata PIC1 of mpc8544), It causes that neither MSI nor MSI-X can work fine. There is a workaround to allow MSI-X to function properly. Signed-off-by: Liu Shuo Signed-off-by: Li Yang --- arch/powerpc/include/asm/mpic.h | 3 ++ arch/powerpc/sysdev/fsl_msi.c | 63 +++++++++++++++++++++++++++++++++++++- arch/powerpc/sysdev/fsl_msi.h | 3 ++ 3 files changed, 67 insertions(+), 2 deletions(-) diff --git a/arch/powerpc/include/asm/mpic.h b/arch/powerpc/include/asm/mpic.h index c9f698a..a9e4f937 100644 --- a/arch/powerpc/include/asm/mpic.h +++ b/arch/powerpc/include/asm/mpic.h @@ -110,6 +110,9 @@ #define MPIC_VECPRI_SENSE_MASK 0x00400000 #define MPIC_IRQ_DESTINATION 0x00010 +#define MPIC_FSL_BRR1 0x00000 +#define MPIC_FSL_BRR1_VER 0x0000ffff + #define MPIC_MAX_IRQ_SOURCES 2048 #define MPIC_MAX_CPUS 32 #define MPIC_MAX_ISU 32 diff --git a/arch/powerpc/sysdev/fsl_msi.c b/arch/powerpc/sysdev/fsl_msi.c index 6e097de..f2d340a 100644 --- a/arch/powerpc/sysdev/fsl_msi.c +++ b/arch/powerpc/sysdev/fsl_msi.c @@ -98,8 +98,23 @@ static int fsl_msi_init_allocator(struct fsl_msi *msi_data) static int fsl_msi_check_device(struct pci_dev *pdev, int nvec, int type) { + struct fsl_msi *msi; + if (type == PCI_CAP_ID_MSIX) pr_debug("fslmsi: MSI-X untested, trying anyway.\n"); + else if (type == PCI_CAP_ID_MSI) { + /* + * MPIC chip with 2.0 version has erratum PIC1. It + * causes that neither MSI nor MSI-X can work fine. + * There is a workaround to allow MSI-X to function + * properly. + */ + list_for_each_entry(msi, &msi_head, list) { + if ((msi->feature & MSI_HW_ERRATA_MASK) + == MSI_HW_ERRATA_ENDIAN) + return -EINVAL; + } + } return 0; } @@ -142,7 +157,11 @@ static void fsl_compose_msi_msg(struct pci_dev *pdev, int hwirq, msg->address_lo = lower_32_bits(address); msg->address_hi = upper_32_bits(address); - msg->data = hwirq; + /* See the comment in fsl_msi_check_device() */ + if ((msi_data->feature & MSI_HW_ERRATA_MASK) == MSI_HW_ERRATA_ENDIAN) + msg->data = __swab32(hwirq); + else + msg->data = hwirq; pr_debug("%s: allocated srs: %d, ibs: %d\n", __func__, hwirq / IRQS_PER_MSI_REG, hwirq % IRQS_PER_MSI_REG); @@ -359,13 +378,43 @@ static int __devinit fsl_msi_setup_hwirq(struct fsl_msi *msi, return 0; } +/* MPIC chip with 2.0 version has erratum PIC1 */ +static int mpic_has_errata(struct platform_device *dev) +{ + struct device_node *mpic_node; + + mpic_node = of_irq_find_parent(dev->dev.of_node); + if (mpic_node) { + u32 *reg_base, brr1 = 0; + /* Get the PIC reg base */ + reg_base = of_iomap(mpic_node, 0); + of_node_put(mpic_node); + if (!reg_base) { + dev_err(&dev->dev, "ioremap problem failed.\n"); + return -EIO; + } + + /* Get the mpic chip version from block revision register 1 */ + brr1 = in_be32(reg_base + MPIC_FSL_BRR1); + iounmap(reg_base); + if ((brr1 & MPIC_FSL_BRR1_VER) == 0x0200) + return 1; + } else { + dev_err(&dev->dev, "MSI can't find his parent mpic node.\n"); + of_node_put(mpic_node); + return -ENODEV; + } + + return 0; +} + static const struct of_device_id fsl_of_msi_ids[]; static int __devinit fsl_of_msi_probe(struct platform_device *dev) { const struct of_device_id *match; struct fsl_msi *msi; struct resource res; - int err, i, j, irq_index, count; + int err, i, j, irq_index, count, errata; int rc; const u32 *p; struct fsl_msi_feature *features; @@ -421,6 +470,16 @@ static int __devinit fsl_of_msi_probe(struct platform_device *dev) msi->feature = features->fsl_pic_ip; + if ((features->fsl_pic_ip & FSL_PIC_IP_MASK) == FSL_PIC_IP_MPIC) { + errata = mpic_has_errata(dev); + if (errata > 0) { + msi->feature |= MSI_HW_ERRATA_ENDIAN; + } else if (errata < 0) { + err = errata; + goto error_out; + } + } + /* * Remember the phandle, so that we can match with any PCI nodes * that have an "fsl,msi" property. diff --git a/arch/powerpc/sysdev/fsl_msi.h b/arch/powerpc/sysdev/fsl_msi.h index 8225f86..354d546 100644 --- a/arch/powerpc/sysdev/fsl_msi.h +++ b/arch/powerpc/sysdev/fsl_msi.h @@ -25,6 +25,9 @@ #define FSL_PIC_IP_IPIC 0x00000002 #define FSL_PIC_IP_VMPIC 0x00000003 +#define MSI_HW_ERRATA_MASK 0x000000F0 +#define MSI_HW_ERRATA_ENDIAN 0x00000010 + struct fsl_msi { struct irq_domain *irqhost;