From patchwork Fri Mar 16 09:31:02 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: chenhui zhao X-Patchwork-Id: 147177 X-Patchwork-Delegate: galak@kernel.crashing.org Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from ozlabs.org (localhost [IPv6:::1]) by ozlabs.org (Postfix) with ESMTP id 0A531B73D4 for ; Fri, 16 Mar 2012 20:30:25 +1100 (EST) Received: from db3outboundpool.messaging.microsoft.com (db3ehsobe004.messaging.microsoft.com [213.199.154.142]) (using TLSv1 with cipher AES128-SHA (128/128 bits)) (Client CN "mail.global.frontbridge.com", Issuer "Microsoft Secure Server Authority" (not verified)) by ozlabs.org (Postfix) with ESMTPS id 1F971B6FD2; Fri, 16 Mar 2012 20:29:00 +1100 (EST) Received: from mail39-db3-R.bigfish.com (10.3.81.225) by DB3EHSOBE005.bigfish.com (10.3.84.25) with Microsoft SMTP Server id 14.1.225.23; Fri, 16 Mar 2012 09:28:57 +0000 Received: from mail39-db3 (localhost [127.0.0.1]) by mail39-db3-R.bigfish.com (Postfix) with ESMTP id 7B4EA440883; Fri, 16 Mar 2012 09:28:57 +0000 (UTC) X-SpamScore: 0 X-BigFish: VS0(zzzz1202hzz8275bhz2dh2a8h668h839hd24h) X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPV:NLI; H:mail.freescale.net; RD:none; EFVD:NLI Received: from mail39-db3 (localhost.localdomain [127.0.0.1]) by mail39-db3 (MessageSwitch) id 133189013629230_16934; Fri, 16 Mar 2012 09:28:56 +0000 (UTC) Received: from DB3EHSMHS018.bigfish.com (unknown [10.3.81.227]) by mail39-db3.bigfish.com (Postfix) with ESMTP id 028F3380045; Fri, 16 Mar 2012 09:28:56 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by DB3EHSMHS018.bigfish.com (10.3.87.118) with Microsoft SMTP Server (TLS) id 14.1.225.23; Fri, 16 Mar 2012 09:28:55 +0000 Received: from az33smr01.freescale.net (10.64.34.199) by 039-SN1MMR1-003.039d.mgd.msft.net (10.84.1.16) with Microsoft SMTP Server id 14.1.355.3; Fri, 16 Mar 2012 04:28:54 -0500 Received: from localhost.localdomain ([10.193.20.166]) by az33smr01.freescale.net (8.13.1/8.13.0) with ESMTP id q2G9Sn9P026351; Fri, 16 Mar 2012 04:28:51 -0500 (CDT) From: Zhao Chenhui To: Subject: [PATCH] fsl_pmc: update device bindings Date: Fri, 16 Mar 2012 17:31:02 +0800 Message-ID: <1331890262-25391-1-git-send-email-chenhui.zhao@freescale.com> X-Mailer: git-send-email 1.6.4.1 MIME-Version: 1.0 X-OriginatorOrg: freescale.com Cc: devicetree-discuss@lists.ozlabs.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Sender: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org From: Li Yang * Added compatible "fsl,p1022-pmc". * Added clock nodes to control the clock of wake-up source. * Used "fsl,pmc-handle" property to connect device and clock node. Signed-off-by: Li Yang Signed-off-by: Zhao Chenhui --- .../devicetree/bindings/powerpc/fsl/pmc.txt | 65 ++++++++++++-------- 1 files changed, 40 insertions(+), 25 deletions(-) diff --git a/Documentation/devicetree/bindings/powerpc/fsl/pmc.txt b/Documentation/devicetree/bindings/powerpc/fsl/pmc.txt index 07256b7..d296e88 100644 --- a/Documentation/devicetree/bindings/powerpc/fsl/pmc.txt +++ b/Documentation/devicetree/bindings/powerpc/fsl/pmc.txt @@ -9,22 +9,26 @@ Properties: "fsl,mpc8548-pmc" should be listed for any chip whose PMC is compatible. "fsl,mpc8536-pmc" should also be listed for any chip - whose PMC is compatible, and implies deep-sleep capability. + whose PMC is compatible, and implies deep-sleep capability and + wake on user defined packet(wakeup on ARP). "fsl,p1022-pmc" + should be listed for any chip whose PMC is compatible, and + implies lossless Ethernet capability during sleep or deep sleep. "fsl,mpc8641d-pmc" should be listed for any chip whose PMC is compatible; all statements below that apply to "fsl,mpc8548-pmc" also apply to "fsl,mpc8641d-pmc". Compatibility does not include bit assignments in SCCR/PMCDR/DEVDISR; these - bit assignments are indicated via the sleep specifier in each device's - sleep property. + bit assignments are indicated via the clock nodes. Device which has a + controllable clock source should have a "fsl,pmc-handle" property pointing + to the clock node. - reg: For devices compatible with "fsl,mpc8349-pmc", the first resource is the PMC block, and the second resource is the Clock Configuration block. - For devices compatible with "fsl,mpc8548-pmc", the first resource - is a 32-byte block beginning with DEVDISR. + For devices compatible with "fsl,mpc8548-pmc", the resource is a 32-byte + block beginning with the register DEVDISR. - interrupts: For "fsl,mpc8349-pmc"-compatible devices, the first resource is the PMC block interrupt. @@ -33,31 +37,42 @@ Properties: this is a phandle to an "fsl,gtm" node on which timer 4 can be used as a wakeup source from deep sleep. -Sleep specifiers: - - fsl,mpc8349-pmc: Sleep specifiers consist of one cell. For each bit - that is set in the cell, the corresponding bit in SCCR will be saved - and cleared on suspend, and restored on resume. This sleep controller - supports disabling and resuming devices at any time. - - fsl,mpc8536-pmc: Sleep specifiers consist of three cells, the third of - which will be ORed into PMCDR upon suspend, and cleared from PMCDR - upon resume. The first two cells are as described for fsl,mpc8578-pmc. - This sleep controller only supports disabling devices during system - sleep, or permanently. +Clock nodes: +The clock nodes are to describe the masks in PM controller registers for each +soc clock. +- fsl,pmcdr-mask: For "fsl,mpc8548-pmc"-compatible devices, some blocks as + wake-up sources can run in low power mode. If a block used as a wake-up + source in low power mode, the corresponding bit in the register PMCDR should + be cleared on suspend and set on resume. If setting bits of the mask, + the corresponding blocks will be used as wake-up sources. - fsl,mpc8548-pmc: Sleep specifiers consist of one or two cells, the - first of which will be ORed into DEVDISR (and the second into - DEVDISR2, if present -- this cell should be zero or absent if the - hardware does not have DEVDISR2) upon a request for permanent device - disabling. This sleep controller does not support configuring devices - to disable during system sleep (unless supported by another compatible - match), or dynamically. +- fsl,sccr-mask: For "fsl,mpc8349-pmc"-compatible devices, the corresponding + bit specified by the mask in SCCR will be saved and cleared on suspend, and + restored on resume. -Example: +- fsl,devdisr-mask: Contain one or two cells, depending on the availability of + DEVDISR2 register. For compatible devices, the mask will be ORed into DEVDISR + or DEVDISR2 when the clock should be permenently disabled. +Example 1: power@b00 { compatible = "fsl,mpc8313-pmc", "fsl,mpc8349-pmc"; reg = <0xb00 0x100 0xa00 0x100>; interrupts = <80 8>; }; + +Example 2: + power@e0070 { + compatible = "fsl,mpc8548-pmc", "fsl,mpc8536-pmc"; + reg = <0xe0070 0x20>; + + etsec1_clk: soc-clk@24 { + fsl,pmcdr-mask = <0x00000080>; + }; + etsec2_clk: soc-clk@25 { + fsl,pmcdr-mask = <0x00000040>; + }; + etsec3_clk: soc-clk@26 { + fsl,pmcdr-mask = <0x00000020>; + }; + };