@@ -37,6 +37,7 @@
#define SVR_8544_E 0x803C01
#define SVR_8545 0x803102
#define SVR_8545_E 0x803902
+#define SVR_8547 0x803101
#define SVR_8547_E 0x803901
#define SVR_8548 0x803100
#define SVR_8548_E 0x803900
@@ -31,6 +31,7 @@
#include <asm/prom.h>
#include <asm/pci-bridge.h>
#include <asm/machdep.h>
+#include <asm/mpc85xx.h>
#include <sysdev/fsl_soc.h>
#include <sysdev/fsl_pci.h>
@@ -426,6 +427,7 @@ int __init fsl_add_bridge(struct device_node *dev, int is_primary)
struct resource rsrc;
const int *bus_range;
u8 progif;
+ u16 temp;
if (!of_device_is_available(dev)) {
pr_warning("%s: disabled\n", dev->full_name);
@@ -476,6 +478,27 @@ int __init fsl_add_bridge(struct device_node *dev, int is_primary)
PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS;
if (fsl_pcie_check_link(hose))
hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK;
+ } else {
+ /*
+ * Set PBFR(PCI Bus Function Register)[10] = 1 to
+ * disable the combining of crossing cacheline
+ * boundary requests into one burst transaction.
+ * PCI-X operation is not affected.
+ * Fix erratum PCI 5 on MPC8548
+ */
+#define PCI_BUS_FUNCTION 0x44
+#define PCI_BUS_FUNCTION_MDS 0x400 /* Master disable streaming */
+ if ((fsl_svr_is(SVR_8543) || fsl_svr_is(SVR_8543_E) ||
+ fsl_svr_is(SVR_8545) || fsl_svr_is(SVR_8545_E) ||
+ fsl_svr_is(SVR_8547) || fsl_svr_is(SVR_8547_E) ||
+ fsl_svr_is(SVR_8548) || fsl_svr_is(SVR_8548_E)) &&
+ !early_find_capability(hose, 0, 0, PCI_CAP_ID_PCIX)) {
+ early_read_config_word(hose, 0, 0,
+ PCI_BUS_FUNCTION, &temp);
+ temp |= PCI_BUS_FUNCTION_MDS;
+ early_write_config_word(hose, 0, 0,
+ PCI_BUS_FUNCTION, temp);
+ }
}
printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx. "