From patchwork Thu Dec 1 07:39:22 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tony Breeds X-Patchwork-Id: 128655 X-Patchwork-Delegate: jwboyer@gmail.com Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from ozlabs.org (localhost [IPv6:::1]) by ozlabs.org (Postfix) with ESMTP id 9D3C6100944 for ; Thu, 1 Dec 2011 18:40:34 +1100 (EST) Received: from localhost.localdomain (ibmaus65.lnk.telstra.net [165.228.126.9]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPSA id 2C0161007D9; Thu, 1 Dec 2011 18:39:38 +1100 (EST) From: Tony Breeds To: Benjamin Herrenschmidt , Josh Boyer Subject: [PATCH 6/8] powerpc/boot: Add mfdcrx Date: Thu, 1 Dec 2011 18:39:22 +1100 Message-Id: <1322725164-4391-7-git-send-email-tony@bakeyournoodle.com> X-Mailer: git-send-email 1.7.6.4 In-Reply-To: <1322725164-4391-1-git-send-email-tony@bakeyournoodle.com> References: <1322725164-4391-1-git-send-email-tony@bakeyournoodle.com> Cc: LinuxPPC-dev X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Sender: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Needed for currituck support. Signed-off-by: Tony Breeds --- arch/powerpc/boot/dcr.h | 6 ++++++ 1 files changed, 6 insertions(+), 0 deletions(-) I chose to use a #define to keep with the style of m[tf]dcr in the same file. diff --git a/arch/powerpc/boot/dcr.h b/arch/powerpc/boot/dcr.h index 645a7c9..cc73f7a 100644 --- a/arch/powerpc/boot/dcr.h +++ b/arch/powerpc/boot/dcr.h @@ -9,6 +9,12 @@ }) #define mtdcr(rn, val) \ asm volatile("mtdcr %0,%1" : : "i"(rn), "r"(val)) +#define mfdcrx(rn) \ + ({ \ + unsigned long rval; \ + asm volatile("mfdcrx %0,%1" : "=r"(rval) : "r"(rn)); \ + rval; \ + }) /* 440GP/440GX SDRAM controller DCRs */ #define DCRN_SDRAM0_CFGADDR 0x010