From patchwork Tue Apr 19 16:59:34 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Meador Inge X-Patchwork-Id: 92035 X-Patchwork-Delegate: benh@kernel.crashing.org Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from ozlabs.org (localhost [IPv6:::1]) by ozlabs.org (Postfix) with ESMTP id AB6B7100B4D for ; Wed, 20 Apr 2011 03:27:14 +1000 (EST) Received: from relay1.mentorg.com (relay1.mentorg.com [192.94.38.131]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "relay1.mentorg.com", Issuer "Entrust Certification Authority - L1B" (not verified)) by ozlabs.org (Postfix) with ESMTPS id 30F64B6F5F; Wed, 20 Apr 2011 03:26:59 +1000 (EST) Received: from svr-orw-exc-10.mgc.mentorg.com ([147.34.98.58]) by relay1.mentorg.com with esmtp id 1QCEHZ-0007ZR-Cb from meador_inge@mentor.com ; Tue, 19 Apr 2011 10:00:09 -0700 Received: from na2-mail.mgc.mentorg.com ([134.86.114.213]) by SVR-ORW-EXC-10.mgc.mentorg.com with Microsoft SMTPSVC(6.0.3790.4675); Tue, 19 Apr 2011 09:56:53 -0700 Received: from localhost.localdomain ([172.30.88.197]) by na2-mail.mgc.mentorg.com with Microsoft SMTPSVC(6.0.3790.3959); Tue, 19 Apr 2011 11:00:07 -0600 From: Meador Inge To: linuxppc-dev@lists.ozlabs.org Subject: [PATCH 1/2] powerpc: document the FSL MPIC message register binding Date: Tue, 19 Apr 2011 11:59:34 -0500 Message-Id: <1303232375-25014-2-git-send-email-meador_inge@mentor.com> X-Mailer: git-send-email 1.6.3.3 In-Reply-To: <1303232375-25014-1-git-send-email-meador_inge@mentor.com> References: <1303232375-25014-1-git-send-email-meador_inge@mentor.com> X-OriginalArrivalTime: 19 Apr 2011 17:00:08.0063 (UTC) FILETIME=[3CAAF8F0:01CBFEB3] Cc: openmcapi-dev@googlegroups.com, devicetree-discuss@lists.ozlabs.org, Hollis Blanchard X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Sender: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org This binding documents how the message register blocks found in some FSL MPIC implementations shall be represented in a device tree. Signed-off-by: Meador Inge Cc: Hollis Blanchard Cc: Grant Likely Cc: Benjamin Herrenschmidt --- .../devicetree/bindings/powerpc/fsl/mpic-msgr.txt | 71 ++++++++++++++++++++ 1 files changed, 71 insertions(+), 0 deletions(-) create mode 100644 Documentation/devicetree/bindings/powerpc/fsl/mpic-msgr.txt diff --git a/Documentation/devicetree/bindings/powerpc/fsl/mpic-msgr.txt b/Documentation/devicetree/bindings/powerpc/fsl/mpic-msgr.txt new file mode 100644 index 0000000..41f1965 --- /dev/null +++ b/Documentation/devicetree/bindings/powerpc/fsl/mpic-msgr.txt @@ -0,0 +1,71 @@ +* FSL MPIC Message Registers + +This binding specifies what properties must be available in the device tree +representation of the message register blocks found in some FSL MPIC +implementations. + +Required properties: + + - compatible: Specifies the compatibility list for the message register + block. The type shall be and the value shall be of the form + "fsl,mpic-v-msgr", where is the version number of + the MPIC containing the message registers. + + - reg: Specifies the base physical address(s) and size(s) of the + message register block's addressable register space. The type shall be + . + + - interrupts: Specifies a list of interrupt source and level-sense pairs. + The type shall be . The length shall be equal to + the number of bits set in the 'msg-receive-mask' property value. + + - interrupt-parent: Specifies the interrupt parent of the message register + block. The type shall be a and the value of that + shall point to the interrupt parent. + +Optional properties: + + - msg-receive-mask: Specifies what registers in the containing block are + allowed to receive interrupts. The value is a bit mask where a set bit + at bit 'n' indicates that message register 'n' can receive interrupts. + The type shall be . The default value shall be + all a string of consecutive ones where the length of the run is equal + to the number of registers in the block. For example, a block with + four registers shall default to 0xF. + +Required alias: + + In order for a message register block to be discovered it *must* define + an alias in the 'aliases' node. Aliases are of the form 'msgr-block', + where is an integer specifying the block's number. Numbers shall start + at 0. + +Example: + + /* The aliases needed to define an order on the message register blocks. + */ + aliases { + msgr-block0 = &msgr_block0; + msgr-block1 = &msgr_block1; + }; + + msgr_block0: msgr-block@41400 { + compatible = "fsl,mpic-v3.1-msgr"; + reg = <0x41400 0x200>; + // Message registers 0 and 3 in this block can receive interrupts on + // sources 0xb0 and 0xb2, respectively. + interrupts = <0xb0 2 0xb2 2>; + msg-receive-mask = <0x5>; + interrupt-parent = <&mpic>; + }; + + msgr_block1: msgr-block@42400 { + compatible = "fsl,mpic-v3.1-msgr"; + reg = <0x42400 0x200>; + // Message registers 0 and 3 in this block can receive interrupts on + // sources 0xb4 and 0xb6, respectively. + interrupts = <0xb4 2 0xb6 2>; + msg-receive-mask = <0x5>; + interrupt-parent = <&mpic>; + }; +