| Message ID | 1294695479-344-7-git-send-email-Joakim.Tjernlund@transmode.se (mailing list archive) |
|---|---|
| State | Not Applicable |
| Headers | show |
diff --git a/arch/ppc/kernel/head_8xx.S b/arch/ppc/kernel/head_8xx.S index 9eb383b..d992c24 100644 --- a/arch/ppc/kernel/head_8xx.S +++ b/arch/ppc/kernel/head_8xx.S @@ -777,12 +777,13 @@ start_here: */ initial_mmu: tlbia /* Invalidate all TLB entries */ -#ifdef CONFIG_PIN_TLB + +/* Always pin the first 8 MB ITLB to prevent ITLB + misses while mucking around with SRR0/SRR1 in asm +*/ lis r8, MI_RSV4I@h ori r8, r8, 0x1c00 -#else - li r8, 0 -#endif + mtspr MI_CTR, r8 /* Set instruction MMU control */ #ifdef CONFIG_PIN_TLB
Various kernel asm modifies SRR0/SRR1 just before executing a rfi. If such code crosses a page boundary you risk a TLB miss which will clobber SRR0/SRR1. Avoid this by always pinning kernel instruction TLB space. Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se> --- arch/ppc/kernel/head_8xx.S | 9 +++++---- 1 files changed, 5 insertions(+), 4 deletions(-)