Show patches with: Submitter = Philippe Bergheaud       |    Archived = No       |   23 patches
Patch Series A/F/R/T S/W/F Date Submitter Delegate State
[v10,2/2] cxl: read PHB indications from the device tree [v10,1/2] powerpc/powernv: Enable tunneled operations - - 2 - --- 2018-03-02 Philippe Bergheaud Accepted
[v10,1/2] powerpc/powernv: Enable tunneled operations [v10,1/2] powerpc/powernv: Enable tunneled operations - - 2 - --- 2018-03-02 Philippe Bergheaud Accepted
[v2] cxl: Use fixed width predefined types in data structure. - - 1 - --- 2016-08-05 Philippe Bergheaud Accepted
[v3] cxl: Refine slice error debug messages 1 - - - --- 2016-07-05 Philippe Bergheaud Accepted
[v2] cxl: Refine slice error debug messages 1 - 1 - --- 2016-07-04 Philippe Bergheaud Changes Requested
[v2] cxl: Ignore CAPI adapters misplaced in switched slots 1 - 1 - --- 2016-07-01 Philippe Bergheaud Accepted
[RESEND,v7,2/2] cxl: Add set and get private data to context struct - - 2 - --- 2016-06-24 Philippe Bergheaud Accepted
[v7,1/2] cxl: Add mechanism for delivering AFU driver specific events - - 1 - --- 2016-06-23 Philippe Bergheaud Accepted
[RESEND,v5,2/2] cxl: Add set and get private data to context struct - - 1 - --- 2016-05-23 Philippe Bergheaud Changes Requested
[v5,1/2] cxl: Add mechanism for delivering AFU driver specific events - - - - --- 2016-05-23 Philippe Bergheaud Changes Requested
cxl: Refine slice error debug messages. 1 - - - --- 2016-05-11 Philippe Bergheaud Changes Requested
[v3,2/2] cxl: Configure the PSL for two CAPI ports on POWER8NVL - - - - --- 2016-03-31 Philippe Bergheaud Accepted
[v3,1/2] powerpc: Define PVR value for POWER8NVL processor - - - - --- 2016-03-31 Philippe Bergheaud Accepted
Added a 5ms wait after a msi-irq is masked - - - - --- 2016-03-22 Philippe Bergheaud Not Applicable
[v2,2/2] cxl: Configure the PSL for two CAPI ports on POWER8NVL 1 - - - --- 2016-03-16 Philippe Bergheaud Changes Requested
[v2,1/2] powerpc: Define PVR value for POWER8NVL processor 1 - - - --- 2016-03-16 Philippe Bergheaud Changes Requested
cxl: Configure the PSL for dual port CAPI on Naples - - - - --- 2016-03-15 Philippe Bergheaud Changes Requested
[RESEND] cxl: Set up and enable PSL Timebase 1 - - - --- 2015-08-28 Philippe Bergheaud Accepted
[V2] cxl: Set up and enable PSL Timebase 1 - - - --- 2015-06-10 Philippe Bergheaud Changes Requested
cxl: Set up and enable PSL Timebase - - - - --- 2015-05-28 Philippe Bergheaud mpe Changes Requested
cxl: Fix a typo in ABI documentation - - - - --- 2015-03-26 Philippe Bergheaud mpe Accepted
Update CXL ABI documentation 1 - - - --- 2014-12-12 Philippe Bergheaud mpe Accepted
powerpc: set default kernel thread priority to medium-low - - - - --- 2013-12-10 Philippe Bergheaud Changes Requested