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Tue, 16 Jul 2024 14:33:48 -0500 From: Stewart Hildebrand To: Bjorn Helgaas , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" , "Michael Ellerman" , Nicholas Piggin , Christophe Leroy , "Naveen N. Rao" , Thomas Zimmermann , "Arnd Bergmann" , Sam Ravnborg , Yongji Xie , =?utf-8?q?Ilpo_J=C3=A4rvinen?= Subject: [PATCH v2 0/8] PCI: Align small (<4k) BARs Date: Tue, 16 Jul 2024 15:32:30 -0400 Message-ID: <20240716193246.1909697-1-stewart.hildebrand@amd.com> X-Mailer: git-send-email 2.45.2 MIME-Version: 1.0 Received-SPF: None (SATLEXMB04.amd.com: stewart.hildebrand@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0001AB52:EE_|DS0PR12MB8220:EE_ X-MS-Office365-Filtering-Correlation-Id: c6b27bc0-1815-4322-0773-08dca5ce384c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|36860700013|1800799024|82310400026|7416014|921020; X-Microsoft-Antispam-Message-Info: COLMGyPoWBIX6dKXpjF5ZkY9S/jC6swul93KXEgkvHAxULSkdVmAvfbJ0zu0Hjwj1BwOpo7RBCbdRz58Ba5Ww2YllC1gUFYmbEmIZ1T9jrlQ/rf8dtFxT4zwIP0ciO3Aa4mtddZ+fs7t6zWdGv4cuStuyLUsy+qZ1S81jwOVDhhdwPewZB2lI8zBvZjI8ZVXcKSMKX5L/W7TqepZMRPdH8K+6cTF4AzDayEMw+7gg8DhZQ8bhH/Z4WGN42frQRWcfseLMicXcR4M1Y8MAIXlXC7WFo6+26iT/iKwvKTPQzbVw0Eek9dBaea9kqER2Zj+Laj785QG4nyuoBLETs1BRO+BAlyQILvEE8h34azhfTxcZkJ8CE79+couOnJsnTn9f3C4DJzUrJJFYcrKUPGb0r+WY4qZ0v4oSbEKxN43Jqqc5asvoooX84Rq4Zqk61Kig2yNHF0hszGVWXVlyF5jmYKiVKP9tN84hXvrIhbJc+6HE/roB7hjLTlBPsYfGrlIBJYWAF7SsjcAcnPAsqgReOgAoPxnY91MzDNT8rMybSxjkOTrFJoMdha6rqDDu/fi3oIecFddxek630dAhYgFaNnMKObQifLWVIK+h1B/lLGIsW/Z4sUb+pO/hUNy4lgoQT7vmWlZLpRJ54hUJZRz5HMzb9xK7LzzvLDCz5Mhjpl9eG9/UFsK5SY+LuZBU4vvVF+IQup4ybHcVbm/0oUWei880rMdbu6/IuhKMni8Z+fmD70p6YGk9DrxYmDA5RRnweeeI+Z/TPBbxd5dnDsiFmO4d59nS9cl3AUje47pachDH8Vsi3po9fX0lRdRm8KhImJPNC7cjxZLxCIt1DmpQFtVJ00Bf4YTPPf/uQ4iIr/fF3jmh2wrHV4jVb7fM+kSiK1h6+SWihE8xspqmF01zEJOtD2PECX7oZv7OwMmZ3nj7zdlGkqQsP32EPDJptDgH6FkIKaaiAmus7SiShZ6B19T9DVwc3roHDrufZH2FslrSETBpdB3EtkgqozQvceBV0rAVtiffE/BhQfbvLyqAV5GUunpduzH3jR+XPufQzFHs/G6L5/YQvIvU4O7xC+6kAXofrXF1I4MIuFg8b+ulmgzBpdNNF3qSbjMdqHCACqLfzwcb0O3P3HweNzMJLQpn6i6B7RAGnpBF71MRITHTv7FCLU5WzFtmam+t9Qzk9JMmp/zR3F/fRUbLHrYTGq9kEi2+DuWbHmSkaAb0mJnaOZyYNfcXZLrSQ6gT5t1alKKgts9eRNy1+T4C56HJ0oai2jbC3WTcNRR9frSci3saHYffhxhnXNBUX51A/2o62ivYuybuFdDHBomVUDGuvE8FtjjGV5C4USBbqHNswWFAac5J05t3TO+f+siquQcgJLM0F4iYRvjPoeGybXaursRHaWBAJSj4yq4iXTa3rlKxg== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(376014)(36860700013)(1800799024)(82310400026)(7416014)(921020);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Jul 2024 19:33:50.5495 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c6b27bc0-1815-4322-0773-08dca5ce384c X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB52.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB8220 X-Mailman-Approved-At: Wed, 17 Jul 2024 09:31:04 +1000 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-pci@vger.kernel.org, x86@kernel.org, linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org, Stewart Hildebrand Errors-To: linuxppc-dev-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" This series sets the default minimum resource alignment to 4k for memory BARs. In preparation, it makes an optimization and addresses some corner cases observed when reallocating BARs. I consider the prepapatory patches to be prerequisites to changing the default BAR alignment. I considered introducing checks for the specific scenarios described, but chose not to pursue this. A check such as "if (xen_domain())" may be pretty simple, but that doesn't account for other hypervisors. If other hypervisors are to be considered, or if we try to dynamically reallocate BARs for devices being marked for passthrough, such a check may quickly grow unwieldy. Further, checking for the MSI-X tables residing in a small (<4k) BAR is unlikely to be a one-liner. Making 4k alignment the default seems more robust. Lastly, when using IORESOURCE_STARTALIGN, all resources in the system need to be aligned. I considered alternatively adding new functionality to the pci=resource_alignment= option, but that approach was already attempted and decided against [1]. [1] https://lore.kernel.org/linux-pci/1473757234-5284-4-git-send-email-xyjxie@linux.vnet.ibm.com/ v1->v2: * rename ("PCI: don't clear already cleared bit") to ("PCI: Don't unnecessarily disable memory decoding") * new patch: ("x86/PCI: Move some logic to new function") * new patch: ("powerpc/pci: Preserve IORESOURCE_STARTALIGN alignment") Stewart Hildebrand (8): x86/PCI: Move some logic to new function PCI: Don't unnecessarily disable memory decoding PCI: Restore resource alignment PCI: Restore memory decoding after reallocation x86/PCI: Preserve IORESOURCE_STARTALIGN alignment powerpc/pci: Preserve IORESOURCE_STARTALIGN alignment PCI: Don't reassign resources that are already aligned PCI: Align small (<4k) BARs arch/powerpc/kernel/pci-common.c | 6 +++-- arch/x86/pci/i386.c | 38 +++++++++++++++------------ drivers/pci/pci.c | 43 +++++++++++++++++++++++-------- drivers/pci/setup-bus.c | 44 ++++++++++++++++++++++++++++++++ include/linux/pci.h | 2 ++ 5 files changed, 103 insertions(+), 30 deletions(-)