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Tue, 25 Oct 2022 04:44:23 +0000 (GMT) Received: from ozlabs.au.ibm.com (unknown [9.192.253.14]) by d06av21.portsmouth.uk.ibm.com (Postfix) with ESMTP id 0BF5E5204F; Tue, 25 Oct 2022 04:44:23 +0000 (GMT) Received: from li-0d7fa1cc-2c9d-11b2-a85c-aed20764436d.ibm.com (haven.au.ibm.com [9.192.254.114]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.au.ibm.com (Postfix) with ESMTPSA id 3A89D600BA; Tue, 25 Oct 2022 15:44:21 +1100 (AEDT) From: Benjamin Gray To: linuxppc-dev@lists.ozlabs.org Subject: [PATCH v9 0/7] Use per-CPU temporary mappings for patching on Radix MMU Date: Tue, 25 Oct 2022 15:44:02 +1100 Message-Id: <20221025044409.448755-1-bgray@linux.ibm.com> X-Mailer: git-send-email 2.37.3 X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: yAEHHCHOvnO_Bo_qAGq2rbzP_6iqu4PM X-Proofpoint-GUID: ln9kUb9cs1TrbRwmt7RScMLOmiUAnVLI X-Proofpoint-UnRewURL: 0 URL was un-rewritten MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-10-24_09,2022-10-21_01,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 bulkscore=0 impostorscore=0 mlxscore=0 spamscore=0 priorityscore=1501 adultscore=0 lowpriorityscore=0 clxscore=1015 phishscore=0 malwarescore=0 mlxlogscore=511 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2209130000 definitions=main-2210250024 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ajd@linux.ibm.com, jniethe5@gmail.com, Benjamin Gray , npiggin@gmail.com, cmr@bluescreens.de Errors-To: linuxppc-dev-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" This is a revision of Chris and Jordan's series to introduce a per-cpu temporary mm to be used for patching with strict rwx on radix mmus. v9: * Fixed patch series name to include "on Radix MMU" again * Renamed breakpoint functions * Introduce patch to gracefully return when patching not possible * Make book3s/32/tlbflush.h TLB page flush implementation a warning * Removed temp_mm_state * Consolidate patching context into single struct shared by both paths Previous versions: v8: https://lore.kernel.org/all/20221021052238.580986-1-bgray@linux.ibm.com/ v7: https://lore.kernel.org/all/20211110003717.1150965-1-jniethe5@gmail.com/ v6: https://lore.kernel.org/all/20210911022904.30962-1-cmr@bluescreens.de/ v5: https://lore.kernel.org/all/20210713053113.4632-1-cmr@linux.ibm.com/ v4: https://lore.kernel.org/all/20210429072057.8870-1-cmr@bluescreens.de/ v3: https://lore.kernel.org/all/20200827052659.24922-1-cmr@codefail.de/ v2: https://lore.kernel.org/all/20200709040316.12789-1-cmr@informatik.wtf/ v1: https://lore.kernel.org/all/20200603051912.23296-1-cmr@informatik.wtf/ RFC: https://lore.kernel.org/all/20200323045205.20314-1-cmr@informatik.wtf/ x86: https://lore.kernel.org/kernel-hardening/20190426232303.28381-1-nadav.amit@gmail.com/ Benjamin Gray (7): powerpc: Allow clearing and restoring registers independent of saved breakpoint state powerpc/code-patching: Handle RWX patching initialisation error powerpc/code-patching: Use WARN_ON and fix check in poking_init powerpc/code-patching: Verify instruction patch succeeded powerpc/tlb: Add local flush for page given mm_struct and psize powerpc/code-patching: Use temporary mm for Radix MMU powerpc/code-patching: Consolidate and cache per-cpu patching context arch/powerpc/include/asm/book3s/32/tlbflush.h | 9 + .../include/asm/book3s/64/tlbflush-hash.h | 5 + arch/powerpc/include/asm/book3s/64/tlbflush.h | 8 + arch/powerpc/include/asm/debug.h | 2 + arch/powerpc/include/asm/nohash/tlbflush.h | 8 + arch/powerpc/kernel/process.c | 38 ++- arch/powerpc/lib/code-patching.c | 252 +++++++++++++++++- 7 files changed, 305 insertions(+), 17 deletions(-) base-commit: 9abf2313adc1ca1b6180c508c25f22f9395cc780 --- 2.37.3