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[115.64.153.41]) by smtp.gmail.com with ESMTPSA id o14sm2856211pfh.145.2021.09.22.07.54.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Sep 2021 07:54:57 -0700 (PDT) From: Nicholas Piggin To: linuxppc-dev@lists.ozlabs.org Subject: [PATCH v3 0/6] powerpc/64s: interrupt speedups Date: Thu, 23 Sep 2021 00:54:46 +1000 Message-Id: <20210922145452.352571-1-npiggin@gmail.com> X-Mailer: git-send-email 2.23.0 MIME-Version: 1.0 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Nicholas Piggin Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" Here's a few stragglers. The first patch was submitted already but had some bugs with unrecoverable exceptions on HPT (current->blah being accessed before MSR[RI] was enabled). Those should be fixed now. The others are generally for helping asynch interrupts, which are a bit harder to measure well but important for IO and IPIs. After this series, the SPR accesses of the interrupt handlers for radix are becoming pretty optimal except for PPR which we could improve on, and virt CPU accounting which is very costly -- we might disable that by default unless someone comes up with a good reason to keep it. Since v1: - Compile fixes for 64e. - Fixed a SOFT_MASK_DEBUG false positive. - Improve function name and comments explaining why patch 2 does not need to hard enable when PMU is enabled via sysfs. Since v2: - Split first patch into patch 1 and 2, improve on the changelogs. - More compile fixes. - Fixed several review comments from Daniel. - Added patch 5. Thanks, Nick Nicholas Piggin (6): powerpc/64/interrupt: make normal synchronous interrupts enable MSR[EE] if possible powerpc/64s/interrupt: handle MSR EE and RI in interrupt entry wrapper powerpc/64s/perf: add power_pmu_wants_prompt_pmi to say whether perf wants PMIs to be soft-NMI powerpc/64s/interrupt: Don't enable MSR[EE] in irq handlers unless perf is in use powerpc/64/interrupt: reduce expensive debug tests powerpc/64s/interrupt: avoid saving CFAR in some asynchronous interrupts arch/powerpc/include/asm/hw_irq.h | 59 +++++++++++++--- arch/powerpc/include/asm/interrupt.h | 58 ++++++++++++--- arch/powerpc/kernel/dbell.c | 3 +- arch/powerpc/kernel/exceptions-64s.S | 101 ++++++++++++++++++--------- arch/powerpc/kernel/fpu.S | 5 ++ arch/powerpc/kernel/irq.c | 3 +- arch/powerpc/kernel/time.c | 31 ++++---- arch/powerpc/kernel/vector.S | 10 +++ arch/powerpc/perf/core-book3s.c | 31 ++++++++ 9 files changed, 232 insertions(+), 69 deletions(-)