diff mbox series

[1/2] pinctrl: tegra: Add descriptions for SoC data fields

Message ID 20250305104939.15168-1-pshete@nvidia.com
State New
Headers show
Series [1/2] pinctrl: tegra: Add descriptions for SoC data fields | expand

Commit Message

Prathamesh Shete March 5, 2025, 10:49 a.m. UTC 
Add detailed descriptions for the remaining fields in the
tegra_pinctrl_soc_data structure. This improves code documentation
and clarifies the purpose of each field, particularly for the
pin-specific configuration options.

Signed-off-by: Prathamesh Shete <pshete@nvidia.com>
---
 drivers/pinctrl/tegra/pinctrl-tegra.h | 26 ++++++++++++++++----------
 1 file changed, 16 insertions(+), 10 deletions(-)

Comments

Linus Walleij March 14, 2025, 10:04 a.m. UTC | #1 
On Wed, Mar 5, 2025 at 11:50 AM Prathamesh Shete <pshete@nvidia.com> wrote:

> Add detailed descriptions for the remaining fields in the
> tegra_pinctrl_soc_data structure. This improves code documentation
> and clarifies the purpose of each field, particularly for the
> pin-specific configuration options.
>
> Signed-off-by: Prathamesh Shete <pshete@nvidia.com>

Both patches applied!

Yours,
Linus Walleij
diff mbox series

Patch

diff --git a/drivers/pinctrl/tegra/pinctrl-tegra.h b/drivers/pinctrl/tegra/pinctrl-tegra.h
index b3289bdf727d..b21f609b5918 100644
--- a/drivers/pinctrl/tegra/pinctrl-tegra.h
+++ b/drivers/pinctrl/tegra/pinctrl-tegra.h
@@ -176,16 +176,22 @@  struct tegra_pingroup {
 
 /**
  * struct tegra_pinctrl_soc_data - Tegra pin controller driver configuration
- * @ngpios:	The number of GPIO pins the pin controller HW affects.
- * @pins:	An array describing all pins the pin controller affects.
- *		All pins which are also GPIOs must be listed first within the
- *		array, and be numbered identically to the GPIO controller's
- *		numbering.
- * @npins:	The numbmer of entries in @pins.
- * @functions:	An array describing all mux functions the SoC supports.
- * @nfunctions:	The numbmer of entries in @functions.
- * @groups:	An array describing all pin groups the pin SoC supports.
- * @ngroups:	The numbmer of entries in @groups.
+ * @ngpios:		The number of GPIO pins the pin controller HW affects.
+ * @gpio_compatible:	Device-tree GPIO compatible string.
+ * @pins:		An array describing all pins the pin controller affects.
+ *			All pins which are also GPIOs must be listed first within the
+ *			array, and be numbered identically to the GPIO controller's
+ *			numbering.
+ * @npins:		The number of entries in @pins.
+ * @functions:		An array describing all mux functions the SoC supports.
+ * @nfunctions:		The number of entries in @functions.
+ * @groups:		An array describing all pin groups the pin SoC supports.
+ * @ngroups:		The number of entries in @groups.
+ * @hsm_in_mux:		High-speed mode field. Only applicable to devices with one pin per group.
+ * @schmitt_in_mux:	Schmitt trigger field. Only applicable to devices with one pin per group.
+ * @drvtype_in_mux:	Drivetype field. Only applicable to devices with one pin per group.
+ * @sfsel_in_mux:	Special function selection field.
+ *			Only applicable to devices with one pin per group.
  */
 struct tegra_pinctrl_soc_data {
 	unsigned ngpios;