diff mbox series

[1/5] i2c: tegra: Add HS mode support

Message ID 20250108110620.86900-2-kkartik@nvidia.com
State New
Headers show
Series Add I2C support for Tegra264 | expand

Commit Message

Kartik Rajput Jan. 8, 2025, 11:06 a.m. UTC
From: Akhil R <akhilrajeev@nvidia.com>

Add support for HS (High Speed) mode tranfers, which is supported by
Tegra194 onwards.

Signed-off-by: Akhil R <akhilrajeev@nvidia.com>
Signed-off-by: Kartik Rajput <kkartik@nvidia.com>
---
 drivers/i2c/busses/i2c-tegra.c | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

Comments

Thierry Reding Jan. 8, 2025, 4:45 p.m. UTC | #1
On Wed, Jan 08, 2025 at 04:36:16PM +0530, Kartik Rajput wrote:
> From: Akhil R <akhilrajeev@nvidia.com>
> 
> Add support for HS (High Speed) mode tranfers, which is supported by
> Tegra194 onwards.
> 
> Signed-off-by: Akhil R <akhilrajeev@nvidia.com>
> Signed-off-by: Kartik Rajput <kkartik@nvidia.com>
> ---
>  drivers/i2c/busses/i2c-tegra.c | 22 ++++++++++++++++++++++
>  1 file changed, 22 insertions(+)
> 
> diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c
> index 87976e99e6d0..7b97c6d347ee 100644
> --- a/drivers/i2c/busses/i2c-tegra.c
> +++ b/drivers/i2c/busses/i2c-tegra.c
> @@ -91,6 +91,7 @@
>  #define I2C_HEADER_IE_ENABLE			BIT(17)
>  #define I2C_HEADER_REPEAT_START			BIT(16)
>  #define I2C_HEADER_CONTINUE_XFER		BIT(15)
> +#define I2C_HEADER_HS_MODE			BIT(22)
>  #define I2C_HEADER_SLAVE_ADDR_SHIFT		1
>  
>  #define I2C_BUS_CLEAR_CNFG			0x084
> @@ -220,10 +221,13 @@ struct tegra_i2c_hw_feature {
>  	u32 thigh_std_mode;
>  	u32 tlow_fast_fastplus_mode;
>  	u32 thigh_fast_fastplus_mode;
> +	u32 tlow_hs_mode;
> +	u32 thigh_hs_mode;
>  	u32 setup_hold_time_std_mode;
>  	u32 setup_hold_time_fast_fast_plus_mode;
>  	u32 setup_hold_time_hs_mode;
>  	bool has_interface_timing_reg;
> +	bool has_hs_mode_support;
>  };
>  
>  /**
> @@ -681,6 +685,18 @@ static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev)
>  	if (i2c_dev->hw->has_interface_timing_reg && tsu_thd)
>  		i2c_writel(i2c_dev, tsu_thd, I2C_INTERFACE_TIMING_1);
>  
> +	/* Write HS mode registers. These will get used only for HS mode*/
> +	if (i2c_dev->hw->has_hs_mode_support) {
> +		tlow = i2c_dev->hw->tlow_hs_mode;
> +		thigh = i2c_dev->hw->thigh_hs_mode;
> +		tsu_thd = i2c_dev->hw->setup_hold_time_hs_mode;
> +
> +		val = FIELD_PREP(I2C_HS_INTERFACE_TIMING_THIGH, thigh) |
> +			FIELD_PREP(I2C_HS_INTERFACE_TIMING_TLOW, tlow);
> +		i2c_writel(i2c_dev, val, I2C_HS_INTERFACE_TIMING_0);
> +		i2c_writel(i2c_dev, tsu_thd, I2C_HS_INTERFACE_TIMING_1);
> +	}
> +
>  	clk_multiplier = (tlow + thigh + 2) * (non_hs_mode + 1);
>  
>  	err = clk_set_rate(i2c_dev->div_clk,
> @@ -1178,6 +1194,9 @@ static void tegra_i2c_push_packet_header(struct tegra_i2c_dev *i2c_dev,
>  	if (msg->flags & I2C_M_RD)
>  		packet_header |= I2C_HEADER_READ;
>  
> +	if (i2c_dev->timings.bus_freq_hz > I2C_MAX_FAST_MODE_PLUS_FREQ)
> +		packet_header |= I2C_HEADER_HS_MODE;
> +

Do we need any kind of checking here? What happens if the requested
frequency is higher than fastmode+ but the device doesn't support the
new high-speed mode? I guess maybe we don't have to care because such
cases won't ever show up because, well, they won't work.

Still, it might be a good idea to be explicit about it and have an extra
check in place (or perhaps a little higher up in the call chain) and
return an error if we're trying to use a frequency that isn't supported
on the chip.

Thierry

>  	if (i2c_dev->dma_mode && !i2c_dev->msg_read)
>  		*dma_buf++ = packet_header;
>  	else
> @@ -1618,10 +1637,13 @@ static const struct tegra_i2c_hw_feature tegra194_i2c_hw = {
>  	.thigh_std_mode = 0x7,
>  	.tlow_fast_fastplus_mode = 0x2,
>  	.thigh_fast_fastplus_mode = 0x2,
> +	.tlow_hs_mode = 0x8,
> +	.thigh_hs_mode = 0x3,
>  	.setup_hold_time_std_mode = 0x08080808,
>  	.setup_hold_time_fast_fast_plus_mode = 0x02020202,
>  	.setup_hold_time_hs_mode = 0x090909,
>  	.has_interface_timing_reg = true,
> +	.has_hs_mode_support = true,
>  };
>  
>  static const struct of_device_id tegra_i2c_of_match[] = {
> -- 
> 2.43.0
>
kernel test robot Jan. 9, 2025, 12:18 p.m. UTC | #2
Hi Kartik,

kernel test robot noticed the following build warnings:

[auto build test WARNING on tegra/for-next]
[also build test WARNING on andi-shyti/i2c/i2c-host robh/for-next linus/master v6.13-rc6 next-20250109]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/Kartik-Rajput/i2c-tegra-Add-HS-mode-support/20250108-190816
base:   https://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux.git for-next
patch link:    https://lore.kernel.org/r/20250108110620.86900-2-kkartik%40nvidia.com
patch subject: [PATCH 1/5] i2c: tegra: Add HS mode support
config: arm-randconfig-001-20250109 (https://download.01.org/0day-ci/archive/20250109/202501091951.yESb0LaA-lkp@intel.com/config)
compiler: arm-linux-gnueabi-gcc (GCC) 14.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20250109/202501091951.yESb0LaA-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202501091951.yESb0LaA-lkp@intel.com/

All warnings (new ones prefixed by >>):

>> drivers/i2c/busses/i2c-tegra.c:231: warning: Function parameter or struct member 'tlow_hs_mode' not described in 'tegra_i2c_hw_feature'
>> drivers/i2c/busses/i2c-tegra.c:231: warning: Function parameter or struct member 'thigh_hs_mode' not described in 'tegra_i2c_hw_feature'
>> drivers/i2c/busses/i2c-tegra.c:231: warning: Function parameter or struct member 'has_hs_mode_support' not described in 'tegra_i2c_hw_feature'
   drivers/i2c/busses/i2c-tegra.c:301: warning: Function parameter or struct member 'dma_dev' not described in 'tegra_i2c_dev'


vim +231 drivers/i2c/busses/i2c-tegra.c

db811ca0f48578 Colin Cross         2011-02-20  163  
6ad068ed63100f Laxman Dewangan     2012-08-19  164  /**
94a5573f0719cf Dmitry Osipenko     2020-09-30  165   * struct tegra_i2c_hw_feature : per hardware generation features
94a5573f0719cf Dmitry Osipenko     2020-09-30  166   * @has_continue_xfer_support: continue-transfer supported
2a2897bab2d3d5 Laxman Dewangan     2013-01-05  167   * @has_per_pkt_xfer_complete_irq: Has enable/disable capability for transfer
94a5573f0719cf Dmitry Osipenko     2020-09-30  168   *		completion interrupt on per packet basis.
6f4664b2e2c2cf Laxman Dewangan     2015-06-30  169   * @has_config_load_reg: Has the config load register to load the new
6f4664b2e2c2cf Laxman Dewangan     2015-06-30  170   *		configuration.
2a2897bab2d3d5 Laxman Dewangan     2013-01-05  171   * @clk_divisor_hs_mode: Clock divisor in HS mode.
0940d24912e925 Sowjanya Komatineni 2019-02-12  172   * @clk_divisor_std_mode: Clock divisor in standard mode. It is
0940d24912e925 Sowjanya Komatineni 2019-02-12  173   *		applicable if there is no fast clock source i.e. single clock
0940d24912e925 Sowjanya Komatineni 2019-02-12  174   *		source.
0940d24912e925 Sowjanya Komatineni 2019-02-12  175   * @clk_divisor_fast_mode: Clock divisor in fast mode. It is
2a2897bab2d3d5 Laxman Dewangan     2013-01-05  176   *		applicable if there is no fast clock source i.e. single clock
2a2897bab2d3d5 Laxman Dewangan     2013-01-05  177   *		source.
0604ee4aefa20f Thierry Reding      2018-12-17  178   * @clk_divisor_fast_plus_mode: Clock divisor in fast mode plus. It is
0604ee4aefa20f Thierry Reding      2018-12-17  179   *		applicable if there is no fast clock source (i.e. single
0604ee4aefa20f Thierry Reding      2018-12-17  180   *		clock source).
0604ee4aefa20f Thierry Reding      2018-12-17  181   * @has_multi_master_mode: The I2C controller supports running in single-master
0604ee4aefa20f Thierry Reding      2018-12-17  182   *		or multi-master mode.
0604ee4aefa20f Thierry Reding      2018-12-17  183   * @has_slcg_override_reg: The I2C controller supports a register that
0604ee4aefa20f Thierry Reding      2018-12-17  184   *		overrides the second level clock gating.
0604ee4aefa20f Thierry Reding      2018-12-17  185   * @has_mst_fifo: The I2C controller contains the new MST FIFO interface that
0604ee4aefa20f Thierry Reding      2018-12-17  186   *		provides additional features and allows for longer messages to
0604ee4aefa20f Thierry Reding      2018-12-17  187   *		be transferred in one go.
94a5573f0719cf Dmitry Osipenko     2020-09-30  188   * @quirks: I2C adapter quirks for limiting write/read transfer size and not
b67d4530cdade7 Sowjanya Komatineni 2019-01-08  189   *		allowing 0 length transfers.
ce9562424501de Sowjanya Komatineni 2019-02-12  190   * @supports_bus_clear: Bus Clear support to recover from bus hang during
ce9562424501de Sowjanya Komatineni 2019-02-12  191   *		SDA stuck low from device for some unknown reasons.
86c92b9965ff17 Sowjanya Komatineni 2019-02-12  192   * @has_apb_dma: Support of APBDMA on corresponding Tegra chip.
0940d24912e925 Sowjanya Komatineni 2019-02-12  193   * @tlow_std_mode: Low period of the clock in standard mode.
0940d24912e925 Sowjanya Komatineni 2019-02-12  194   * @thigh_std_mode: High period of the clock in standard mode.
0940d24912e925 Sowjanya Komatineni 2019-02-12  195   * @tlow_fast_fastplus_mode: Low period of the clock in fast/fast-plus modes.
0940d24912e925 Sowjanya Komatineni 2019-02-12  196   * @thigh_fast_fastplus_mode: High period of the clock in fast/fast-plus modes.
0940d24912e925 Sowjanya Komatineni 2019-02-12  197   * @setup_hold_time_std_mode: Setup and hold time for start and stop conditions
0940d24912e925 Sowjanya Komatineni 2019-02-12  198   *		in standard mode.
0940d24912e925 Sowjanya Komatineni 2019-02-12  199   * @setup_hold_time_fast_fast_plus_mode: Setup and hold time for start and stop
0940d24912e925 Sowjanya Komatineni 2019-02-12  200   *		conditions in fast/fast-plus modes.
0940d24912e925 Sowjanya Komatineni 2019-02-12  201   * @setup_hold_time_hs_mode: Setup and hold time for start and stop conditions
0940d24912e925 Sowjanya Komatineni 2019-02-12  202   *		in HS mode.
0940d24912e925 Sowjanya Komatineni 2019-02-12  203   * @has_interface_timing_reg: Has interface timing register to program the tuned
0940d24912e925 Sowjanya Komatineni 2019-02-12  204   *		timing settings.
6ad068ed63100f Laxman Dewangan     2012-08-19  205   */
6ad068ed63100f Laxman Dewangan     2012-08-19  206  struct tegra_i2c_hw_feature {
6ad068ed63100f Laxman Dewangan     2012-08-19  207  	bool has_continue_xfer_support;
2a2897bab2d3d5 Laxman Dewangan     2013-01-05  208  	bool has_per_pkt_xfer_complete_irq;
6f4664b2e2c2cf Laxman Dewangan     2015-06-30  209  	bool has_config_load_reg;
f1c2ff98065dce Dmitry Osipenko     2020-09-30  210  	u32 clk_divisor_hs_mode;
f1c2ff98065dce Dmitry Osipenko     2020-09-30  211  	u32 clk_divisor_std_mode;
f1c2ff98065dce Dmitry Osipenko     2020-09-30  212  	u32 clk_divisor_fast_mode;
f1c2ff98065dce Dmitry Osipenko     2020-09-30  213  	u32 clk_divisor_fast_plus_mode;
497fbe24987bd2 Shardar Shariff Md  2016-03-14  214  	bool has_multi_master_mode;
497fbe24987bd2 Shardar Shariff Md  2016-03-14  215  	bool has_slcg_override_reg;
c5907c6b96f187 Thierry Reding      2018-06-19  216  	bool has_mst_fifo;
b67d4530cdade7 Sowjanya Komatineni 2019-01-08  217  	const struct i2c_adapter_quirks *quirks;
ce9562424501de Sowjanya Komatineni 2019-02-12  218  	bool supports_bus_clear;
86c92b9965ff17 Sowjanya Komatineni 2019-02-12  219  	bool has_apb_dma;
f1c2ff98065dce Dmitry Osipenko     2020-09-30  220  	u32 tlow_std_mode;
f1c2ff98065dce Dmitry Osipenko     2020-09-30  221  	u32 thigh_std_mode;
f1c2ff98065dce Dmitry Osipenko     2020-09-30  222  	u32 tlow_fast_fastplus_mode;
f1c2ff98065dce Dmitry Osipenko     2020-09-30  223  	u32 thigh_fast_fastplus_mode;
19a765ab587022 Akhil R             2025-01-08  224  	u32 tlow_hs_mode;
19a765ab587022 Akhil R             2025-01-08  225  	u32 thigh_hs_mode;
0940d24912e925 Sowjanya Komatineni 2019-02-12  226  	u32 setup_hold_time_std_mode;
0940d24912e925 Sowjanya Komatineni 2019-02-12  227  	u32 setup_hold_time_fast_fast_plus_mode;
0940d24912e925 Sowjanya Komatineni 2019-02-12  228  	u32 setup_hold_time_hs_mode;
0940d24912e925 Sowjanya Komatineni 2019-02-12  229  	bool has_interface_timing_reg;
19a765ab587022 Akhil R             2025-01-08  230  	bool has_hs_mode_support;
6ad068ed63100f Laxman Dewangan     2012-08-19 @231  };
6ad068ed63100f Laxman Dewangan     2012-08-19  232
Kartik Rajput Jan. 15, 2025, 11:40 a.m. UTC | #3
On Wed, 2025-01-08 at 17:45 +0100, Thierry Reding wrote:
> On Wed, Jan 08, 2025 at 04:36:16PM +0530, Kartik Rajput wrote:
> > From: Akhil R <akhilrajeev@nvidia.com>
> > 
> > Add support for HS (High Speed) mode tranfers, which is supported
> > by
> > Tegra194 onwards.
> > 
> > Signed-off-by: Akhil R <akhilrajeev@nvidia.com>
> > Signed-off-by: Kartik Rajput <kkartik@nvidia.com>
> > ---
> >  drivers/i2c/busses/i2c-tegra.c | 22 ++++++++++++++++++++++
> >  1 file changed, 22 insertions(+)
> > 
> > diff --git a/drivers/i2c/busses/i2c-tegra.c
> > b/drivers/i2c/busses/i2c-tegra.c
> > index 87976e99e6d0..7b97c6d347ee 100644
> > --- a/drivers/i2c/busses/i2c-tegra.c
> > +++ b/drivers/i2c/busses/i2c-tegra.c
> > @@ -91,6 +91,7 @@
> >  #define I2C_HEADER_IE_ENABLE                   BIT(17)
> >  #define I2C_HEADER_REPEAT_START                        BIT(16)
> >  #define I2C_HEADER_CONTINUE_XFER               BIT(15)
> > +#define I2C_HEADER_HS_MODE                     BIT(22)
> >  #define I2C_HEADER_SLAVE_ADDR_SHIFT            1
> >  
> >  #define I2C_BUS_CLEAR_CNFG                     0x084
> > @@ -220,10 +221,13 @@ struct tegra_i2c_hw_feature {
> >         u32 thigh_std_mode;
> >         u32 tlow_fast_fastplus_mode;
> >         u32 thigh_fast_fastplus_mode;
> > +       u32 tlow_hs_mode;
> > +       u32 thigh_hs_mode;
> >         u32 setup_hold_time_std_mode;
> >         u32 setup_hold_time_fast_fast_plus_mode;
> >         u32 setup_hold_time_hs_mode;
> >         bool has_interface_timing_reg;
> > +       bool has_hs_mode_support;
> >  };
> >  
> >  /**
> > @@ -681,6 +685,18 @@ static int tegra_i2c_init(struct tegra_i2c_dev
> > *i2c_dev)
> >         if (i2c_dev->hw->has_interface_timing_reg && tsu_thd)
> >                 i2c_writel(i2c_dev, tsu_thd,
> > I2C_INTERFACE_TIMING_1);
> >  
> > +       /* Write HS mode registers. These will get used only for HS
> > mode*/
> > +       if (i2c_dev->hw->has_hs_mode_support) {
> > +               tlow = i2c_dev->hw->tlow_hs_mode;
> > +               thigh = i2c_dev->hw->thigh_hs_mode;
> > +               tsu_thd = i2c_dev->hw->setup_hold_time_hs_mode;
> > +
> > +               val = FIELD_PREP(I2C_HS_INTERFACE_TIMING_THIGH,
> > thigh) |
> > +                       FIELD_PREP(I2C_HS_INTERFACE_TIMING_TLOW,
> > tlow);
> > +               i2c_writel(i2c_dev, val,
> > I2C_HS_INTERFACE_TIMING_0);
> > +               i2c_writel(i2c_dev, tsu_thd,
> > I2C_HS_INTERFACE_TIMING_1);
> > +       }
> > +
> >         clk_multiplier = (tlow + thigh + 2) * (non_hs_mode + 1);
> >  
> >         err = clk_set_rate(i2c_dev->div_clk,
> > @@ -1178,6 +1194,9 @@ static void
> > tegra_i2c_push_packet_header(struct tegra_i2c_dev *i2c_dev,
> >         if (msg->flags & I2C_M_RD)
> >                 packet_header |= I2C_HEADER_READ;
> >  
> > +       if (i2c_dev->timings.bus_freq_hz >
> > I2C_MAX_FAST_MODE_PLUS_FREQ)
> > +               packet_header |= I2C_HEADER_HS_MODE;
> > +
> 
> Do we need any kind of checking here? What happens if the requested
> frequency is higher than fastmode+ but the device doesn't support the
> new high-speed mode? I guess maybe we don't have to care because such
> cases won't ever show up because, well, they won't work.
> 
> Still, it might be a good idea to be explicit about it and have an
> extra
> check in place (or perhaps a little higher up in the call chain) and
> return an error if we're trying to use a frequency that isn't
> supported
> on the chip.
> 
> Thierry

ACK. I will add a check for this.

> 
> >         if (i2c_dev->dma_mode && !i2c_dev->msg_read)
> >                 *dma_buf++ = packet_header;
> >         else
> > @@ -1618,10 +1637,13 @@ static const struct tegra_i2c_hw_feature
> > tegra194_i2c_hw = {
> >         .thigh_std_mode = 0x7,
> >         .tlow_fast_fastplus_mode = 0x2,
> >         .thigh_fast_fastplus_mode = 0x2,
> > +       .tlow_hs_mode = 0x8,
> > +       .thigh_hs_mode = 0x3,
> >         .setup_hold_time_std_mode = 0x08080808,
> >         .setup_hold_time_fast_fast_plus_mode = 0x02020202,
> >         .setup_hold_time_hs_mode = 0x090909,
> >         .has_interface_timing_reg = true,
> > +       .has_hs_mode_support = true,
> >  };
> >  
> >  static const struct of_device_id tegra_i2c_of_match[] = {
> > -- 
> > 2.43.0
> >
diff mbox series

Patch

diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c
index 87976e99e6d0..7b97c6d347ee 100644
--- a/drivers/i2c/busses/i2c-tegra.c
+++ b/drivers/i2c/busses/i2c-tegra.c
@@ -91,6 +91,7 @@ 
 #define I2C_HEADER_IE_ENABLE			BIT(17)
 #define I2C_HEADER_REPEAT_START			BIT(16)
 #define I2C_HEADER_CONTINUE_XFER		BIT(15)
+#define I2C_HEADER_HS_MODE			BIT(22)
 #define I2C_HEADER_SLAVE_ADDR_SHIFT		1
 
 #define I2C_BUS_CLEAR_CNFG			0x084
@@ -220,10 +221,13 @@  struct tegra_i2c_hw_feature {
 	u32 thigh_std_mode;
 	u32 tlow_fast_fastplus_mode;
 	u32 thigh_fast_fastplus_mode;
+	u32 tlow_hs_mode;
+	u32 thigh_hs_mode;
 	u32 setup_hold_time_std_mode;
 	u32 setup_hold_time_fast_fast_plus_mode;
 	u32 setup_hold_time_hs_mode;
 	bool has_interface_timing_reg;
+	bool has_hs_mode_support;
 };
 
 /**
@@ -681,6 +685,18 @@  static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev)
 	if (i2c_dev->hw->has_interface_timing_reg && tsu_thd)
 		i2c_writel(i2c_dev, tsu_thd, I2C_INTERFACE_TIMING_1);
 
+	/* Write HS mode registers. These will get used only for HS mode*/
+	if (i2c_dev->hw->has_hs_mode_support) {
+		tlow = i2c_dev->hw->tlow_hs_mode;
+		thigh = i2c_dev->hw->thigh_hs_mode;
+		tsu_thd = i2c_dev->hw->setup_hold_time_hs_mode;
+
+		val = FIELD_PREP(I2C_HS_INTERFACE_TIMING_THIGH, thigh) |
+			FIELD_PREP(I2C_HS_INTERFACE_TIMING_TLOW, tlow);
+		i2c_writel(i2c_dev, val, I2C_HS_INTERFACE_TIMING_0);
+		i2c_writel(i2c_dev, tsu_thd, I2C_HS_INTERFACE_TIMING_1);
+	}
+
 	clk_multiplier = (tlow + thigh + 2) * (non_hs_mode + 1);
 
 	err = clk_set_rate(i2c_dev->div_clk,
@@ -1178,6 +1194,9 @@  static void tegra_i2c_push_packet_header(struct tegra_i2c_dev *i2c_dev,
 	if (msg->flags & I2C_M_RD)
 		packet_header |= I2C_HEADER_READ;
 
+	if (i2c_dev->timings.bus_freq_hz > I2C_MAX_FAST_MODE_PLUS_FREQ)
+		packet_header |= I2C_HEADER_HS_MODE;
+
 	if (i2c_dev->dma_mode && !i2c_dev->msg_read)
 		*dma_buf++ = packet_header;
 	else
@@ -1618,10 +1637,13 @@  static const struct tegra_i2c_hw_feature tegra194_i2c_hw = {
 	.thigh_std_mode = 0x7,
 	.tlow_fast_fastplus_mode = 0x2,
 	.thigh_fast_fastplus_mode = 0x2,
+	.tlow_hs_mode = 0x8,
+	.thigh_hs_mode = 0x3,
 	.setup_hold_time_std_mode = 0x08080808,
 	.setup_hold_time_fast_fast_plus_mode = 0x02020202,
 	.setup_hold_time_hs_mode = 0x090909,
 	.has_interface_timing_reg = true,
+	.has_hs_mode_support = true,
 };
 
 static const struct of_device_id tegra_i2c_of_match[] = {