| Message ID | d6be5236ab4ff5b5fde78004c38d8bced42f2ba2.1739784071.git.zhoubinbin@loongson.cn |
|---|---|
| State | Changes Requested |
| Headers | show |
| Series | pwm: Introduce pwm driver for the Loongson family chips | expand |
On Mon, Feb 17, 2025 at 05:30:24PM +0800, Binbin Zhou wrote: > Add Loongson PWM controller binding with DT schema format using > json-schema. > > Signed-off-by: Binbin Zhou <zhoubinbin@loongson.cn> > Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> > Acked-by: Huacai Chen <chenhuacai@loongson.cn> nitpick: Please put your S-o-b last. > --- > .../bindings/pwm/loongson,ls7a-pwm.yaml | 66 +++++++++++++++++++ > MAINTAINERS | 6 ++ > 2 files changed, 72 insertions(+) > create mode 100644 Documentation/devicetree/bindings/pwm/loongson,ls7a-pwm.yaml > > diff --git a/Documentation/devicetree/bindings/pwm/loongson,ls7a-pwm.yaml b/Documentation/devicetree/bindings/pwm/loongson,ls7a-pwm.yaml > new file mode 100644 > index 000000000000..46814773e0cc > --- /dev/null > +++ b/Documentation/devicetree/bindings/pwm/loongson,ls7a-pwm.yaml > @@ -0,0 +1,66 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/pwm/loongson,ls7a-pwm.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Loongson PWM Controller > + > +maintainers: > + - Binbin Zhou <zhoubinbin@loongson.cn> > + > +description: > + The Loongson PWM has one pulse width output signal and one pulse input > + signal to be measured. > + It can be found on Loongson-2K series cpus and Loongson LS7A bridge chips. > + > +allOf: > + - $ref: pwm.yaml# > + > +properties: > + compatible: > + oneOf: > + - const: loongson,ls7a-pwm > + - items: > + - enum: > + - loongson,ls2k0500-pwm > + - loongson,ls2k1000-pwm > + - loongson,ls2k2000-pwm > + - const: loongson,ls7a-pwm > + > + reg: > + maxItems: 1 > + > + interrupts: > + maxItems: 1 > + > + clocks: > + maxItems: 1 > + > + '#pwm-cells': > + description: > + The first cell must have a value of 0, which specifies the PWM output signal; > + The second cell is the period in nanoseconds; > + The third cell flag supported by this binding is PWM_POLARITY_INVERTED. > + const: 3 > + > +required: > + - compatible > + - reg > + - interrupts > + - clocks > + > +additionalProperties: false > + > +examples: > + - | > + #include <dt-bindings/interrupt-controller/irq.h> > + #include <dt-bindings/clock/loongson,ls2k-clk.h> > + pwm@1fe22000 { Another nitpick: I would have added another \n between the includes and the dt node. Looking at the output of `git grep -A1 \#include Documentation/devicetree/bindings/pwm/` this isn't consistent, but the empty line is the more usual approach. I'll look into the 2nd patch and if these two nitpicks are the only concerns left, I'll fixup accordingly unless you object. Best regards Uwe
diff --git a/Documentation/devicetree/bindings/pwm/loongson,ls7a-pwm.yaml b/Documentation/devicetree/bindings/pwm/loongson,ls7a-pwm.yaml new file mode 100644 index 000000000000..46814773e0cc --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/loongson,ls7a-pwm.yaml @@ -0,0 +1,66 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/loongson,ls7a-pwm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Loongson PWM Controller + +maintainers: + - Binbin Zhou <zhoubinbin@loongson.cn> + +description: + The Loongson PWM has one pulse width output signal and one pulse input + signal to be measured. + It can be found on Loongson-2K series cpus and Loongson LS7A bridge chips. + +allOf: + - $ref: pwm.yaml# + +properties: + compatible: + oneOf: + - const: loongson,ls7a-pwm + - items: + - enum: + - loongson,ls2k0500-pwm + - loongson,ls2k1000-pwm + - loongson,ls2k2000-pwm + - const: loongson,ls7a-pwm + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + '#pwm-cells': + description: + The first cell must have a value of 0, which specifies the PWM output signal; + The second cell is the period in nanoseconds; + The third cell flag supported by this binding is PWM_POLARITY_INVERTED. + const: 3 + +required: + - compatible + - reg + - interrupts + - clocks + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/clock/loongson,ls2k-clk.h> + pwm@1fe22000 { + compatible = "loongson,ls2k1000-pwm", "loongson,ls7a-pwm"; + reg = <0x1fe22000 0x10>; + interrupt-parent = <&liointc0>; + interrupts = <24 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk LOONGSON2_APB_CLK>; + #pwm-cells = <3>; + }; diff --git a/MAINTAINERS b/MAINTAINERS index 896a307fa065..9fcde52aec4b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -13616,6 +13616,12 @@ S: Maintained F: Documentation/devicetree/bindings/i2c/loongson,ls2x-i2c.yaml F: drivers/i2c/busses/i2c-ls2x.c +LOONGSON PWM DRIVER +M: Binbin Zhou <zhoubinbin@loongson.cn> +L: linux-pwm@vger.kernel.org +S: Maintained +F: Documentation/devicetree/bindings/pwm/loongson,ls7a-pwm.yaml + LOONGSON-2 SOC SERIES CLOCK DRIVER M: Yinbo Zhu <zhuyinbo@loongson.cn> L: linux-clk@vger.kernel.org