Message ID | bbb573658f02c5a373eca1fe3f55ef40b09c7a57.1731303328.git.unicorn_wang@outlook.com |
---|---|
State | New |
Headers | show
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Sun, 10 Nov 2024 22:01:02 -0800 (PST) Received: from localhost.localdomain ([122.8.183.87]) by smtp.gmail.com with ESMTPSA id 46e09a7af769-71a107ebea1sm2125973a34.14.2024.11.10.22.00.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 10 Nov 2024 22:01:01 -0800 (PST) From: Chen Wang <unicornxw@gmail.com> To: kw@linux.com, u.kleine-koenig@baylibre.com, aou@eecs.berkeley.edu, arnd@arndb.de, bhelgaas@google.com, unicorn_wang@outlook.com, conor+dt@kernel.org, guoren@kernel.org, inochiama@outlook.com, krzk+dt@kernel.org, lee@kernel.org, lpieralisi@kernel.org, manivannan.sadhasivam@linaro.org, palmer@dabbelt.com, paul.walmsley@sifive.com, pbrobinson@gmail.com, robh@kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, linux-riscv@lists.infradead.org, chao.wei@sophgo.com, xiaoguang.xing@sophgo.com, fengchun.li@sophgo.com Subject: [PATCH 5/5] riscv: sophgo: dts: enable pcie for PioneerBox Date: Mon, 11 Nov 2024 14:00:53 +0800 Message-Id: <bbb573658f02c5a373eca1fe3f55ef40b09c7a57.1731303328.git.unicorn_wang@outlook.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <cover.1731303328.git.unicorn_wang@outlook.com> References: <cover.1731303328.git.unicorn_wang@outlook.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: <linux-pci.vger.kernel.org> List-Subscribe: <mailto:linux-pci+subscribe@vger.kernel.org> List-Unsubscribe: <mailto:linux-pci+unsubscribe@vger.kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit |
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Add PCIe support to Sophgo SG2042 SoC
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diff --git a/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts b/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts index a3f9d6f22566..746b9c3d254c 100644 --- a/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts +++ b/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts @@ -45,6 +45,18 @@ mcu: syscon@17 { }; }; +&pcie_rc0 { + status = "okay"; +}; + +&pcie_rc1 { + status = "okay"; +}; + +&pcie_rc2 { + status = "okay"; +}; + &sd { bus-width = <4>; no-sdio;