Message ID | 4f030066767c2a3b3acabe24e3dfbb8d87b42bfe.1731303328.git.unicorn_wang@outlook.com |
---|---|
State | New |
Headers | show |
Series | Add PCIe support to Sophgo SG2042 SoC | expand |
On Mon, 11 Nov 2024 14:00:15 +0800, Chen Wang wrote: > From: Chen Wang <unicorn_wang@outlook.com> > > Document SOPHGO SG2042 compatible for PCIe control registers. > These registers are shared by pcie controller nodes. > > Signed-off-by: Chen Wang <unicorn_wang@outlook.com> > --- > Documentation/devicetree/bindings/mfd/syscon.yaml | 2 ++ > 1 file changed, 2 insertions(+) > Acked-by: Rob Herring (Arm) <robh@kernel.org>
diff --git a/Documentation/devicetree/bindings/mfd/syscon.yaml b/Documentation/devicetree/bindings/mfd/syscon.yaml index cc9b17ad69f2..55f919690001 100644 --- a/Documentation/devicetree/bindings/mfd/syscon.yaml +++ b/Documentation/devicetree/bindings/mfd/syscon.yaml @@ -106,6 +106,7 @@ select: - rockchip,rk3576-qos - rockchip,rk3588-qos - rockchip,rv1126-qos + - sophgo,sg2042-pcie-ctrl - st,spear1340-misc - stericsson,nomadik-pmu - starfive,jh7100-sysmain @@ -203,6 +204,7 @@ properties: - rockchip,rk3576-qos - rockchip,rk3588-qos - rockchip,rv1126-qos + - sophgo,sg2042-pcie-ctrl - st,spear1340-misc - stericsson,nomadik-pmu - starfive,jh7100-sysmain