| Message ID | 20241130-pcie-en7581-fixes-v5-5-dbffe41566b3@kernel.org |
|---|---|
| State | New |
| Headers | show |
| Series | PCI: mediatek-gen3: mtk_pcie_en7581_power_up() code refactoring | expand |
If you repost this series, here are a few comments/typos. Otherwise we can do the trivial updates on the branch. In subject: this patch doesn't *add* a delay; it *moves* it. On Sat, Nov 30, 2024 at 12:20:14AM +0100, Lorenzo Bianconi wrote: > Airoha EN7581 has a hw bug asserting/releasing PCIE_PE_RSTB signal > causing occasional PCIe link down issues. In order to overcome the > problem, PCIe block is reset using REG_PCI_CONTROL (0x88) and > REG_RESET_CONTROL (0x834) registers available in the clock module > running clk_bulk_prepare_enable in mtk_pcie_en7581_power_up(). Add parens after clk_bulk_prepare_enable. > In order to make the code more readable, move the wait for the time > needed to complete the PCIe reset from en7581_pci_enable() to > mtk_pcie_en7581_power_up(). > Reduce reset timeout from 250ms to the standard PCIE_T_PVPERL_MS value > (100ms) since it has no impact on the driver behavior. > > Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> > Acked-by: Stephen Boyd <sboyd@kernel.org> > Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> > Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org> > --- > drivers/clk/clk-en7523.c | 1 - > drivers/pci/controller/pcie-mediatek-gen3.c | 7 +++++++ > 2 files changed, 7 insertions(+), 1 deletion(-) > > diff --git a/drivers/clk/clk-en7523.c b/drivers/clk/clk-en7523.c > index 22fbea61c3dcc05e63f8fa37e203c62b2a6fe79e..bf9d9594bef8a54316e28e56a1642ecb0562377a 100644 > --- a/drivers/clk/clk-en7523.c > +++ b/drivers/clk/clk-en7523.c > @@ -393,7 +393,6 @@ static int en7581_pci_enable(struct clk_hw *hw) > REG_PCI_CONTROL_PERSTOUT; > val = readl(np_base + REG_PCI_CONTROL); > writel(val | mask, np_base + REG_PCI_CONTROL); > - msleep(250); > > return 0; > } > diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/controller/pcie-mediatek-gen3.c > index 01e8fde96080fa55f6c23c7d1baab6e22c49fcff..da01e741ff290464d28e172879520dbe0670cc41 100644 > --- a/drivers/pci/controller/pcie-mediatek-gen3.c > +++ b/drivers/pci/controller/pcie-mediatek-gen3.c > @@ -977,6 +977,13 @@ static int mtk_pcie_en7581_power_up(struct mtk_gen3_pcie *pcie) > goto err_clk_prepare_enable; > } > > + /* > + * Airoha EN7581 performs PCIe reset via clk callabacks since it has a > + * hw issue with PCIE_PE_RSTB signal. Add wait for the time needed to > + * complete the PCIe reset. s/callabacks/callbacks/ > + */ > + msleep(PCIE_T_PVPERL_MS); > + > return 0; > > err_clk_prepare_enable: > > -- > 2.47.0 >
> > If you repost this series, here are a few comments/typos. Otherwise > we can do the trivial updates on the branch. > > In subject: this patch doesn't *add* a delay; it *moves* it. ack, I will fix it. > > On Sat, Nov 30, 2024 at 12:20:14AM +0100, Lorenzo Bianconi wrote: > > Airoha EN7581 has a hw bug asserting/releasing PCIE_PE_RSTB signal > > causing occasional PCIe link down issues. In order to overcome the > > problem, PCIe block is reset using REG_PCI_CONTROL (0x88) and > > REG_RESET_CONTROL (0x834) registers available in the clock module > > running clk_bulk_prepare_enable in mtk_pcie_en7581_power_up(). > > Add parens after clk_bulk_prepare_enable. ack, I will fix it. > > > In order to make the code more readable, move the wait for the time > > needed to complete the PCIe reset from en7581_pci_enable() to > > mtk_pcie_en7581_power_up(). > > Reduce reset timeout from 250ms to the standard PCIE_T_PVPERL_MS value > > (100ms) since it has no impact on the driver behavior. > > > > Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> > > Acked-by: Stephen Boyd <sboyd@kernel.org> > > Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> > > Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org> > > --- > > drivers/clk/clk-en7523.c | 1 - > > drivers/pci/controller/pcie-mediatek-gen3.c | 7 +++++++ > > 2 files changed, 7 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/clk/clk-en7523.c b/drivers/clk/clk-en7523.c > > index 22fbea61c3dcc05e63f8fa37e203c62b2a6fe79e..bf9d9594bef8a54316e28e56a1642ecb0562377a 100644 > > --- a/drivers/clk/clk-en7523.c > > +++ b/drivers/clk/clk-en7523.c > > @@ -393,7 +393,6 @@ static int en7581_pci_enable(struct clk_hw *hw) > > REG_PCI_CONTROL_PERSTOUT; > > val = readl(np_base + REG_PCI_CONTROL); > > writel(val | mask, np_base + REG_PCI_CONTROL); > > - msleep(250); > > > > return 0; > > } > > diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/controller/pcie-mediatek-gen3.c > > index 01e8fde96080fa55f6c23c7d1baab6e22c49fcff..da01e741ff290464d28e172879520dbe0670cc41 100644 > > --- a/drivers/pci/controller/pcie-mediatek-gen3.c > > +++ b/drivers/pci/controller/pcie-mediatek-gen3.c > > @@ -977,6 +977,13 @@ static int mtk_pcie_en7581_power_up(struct mtk_gen3_pcie *pcie) > > goto err_clk_prepare_enable; > > } > > > > + /* > > + * Airoha EN7581 performs PCIe reset via clk callabacks since it has a > > + * hw issue with PCIE_PE_RSTB signal. Add wait for the time needed to > > + * complete the PCIe reset. > > s/callabacks/callbacks/ ack, I will fix it. Regards, Lorenzo > > > + */ > > + msleep(PCIE_T_PVPERL_MS); > > + > > return 0; > > > > err_clk_prepare_enable: > > > > -- > > 2.47.0 > >
diff --git a/drivers/clk/clk-en7523.c b/drivers/clk/clk-en7523.c index 22fbea61c3dcc05e63f8fa37e203c62b2a6fe79e..bf9d9594bef8a54316e28e56a1642ecb0562377a 100644 --- a/drivers/clk/clk-en7523.c +++ b/drivers/clk/clk-en7523.c @@ -393,7 +393,6 @@ static int en7581_pci_enable(struct clk_hw *hw) REG_PCI_CONTROL_PERSTOUT; val = readl(np_base + REG_PCI_CONTROL); writel(val | mask, np_base + REG_PCI_CONTROL); - msleep(250); return 0; } diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/controller/pcie-mediatek-gen3.c index 01e8fde96080fa55f6c23c7d1baab6e22c49fcff..da01e741ff290464d28e172879520dbe0670cc41 100644 --- a/drivers/pci/controller/pcie-mediatek-gen3.c +++ b/drivers/pci/controller/pcie-mediatek-gen3.c @@ -977,6 +977,13 @@ static int mtk_pcie_en7581_power_up(struct mtk_gen3_pcie *pcie) goto err_clk_prepare_enable; } + /* + * Airoha EN7581 performs PCIe reset via clk callabacks since it has a + * hw issue with PCIE_PE_RSTB signal. Add wait for the time needed to + * complete the PCIe reset. + */ + msleep(PCIE_T_PVPERL_MS); + return 0; err_clk_prepare_enable: