| Message ID | 20241030104717.88688-3-bastien.curutchet@bootlin.com |
|---|---|
| State | New |
| Headers | show |
| Series | Implement setup_inteface() in the DaVinci NAND controller | expand |
Hi Bastien, kernel test robot noticed the following build warnings: [auto build test WARNING on krzk-mem-ctrl/for-next] [also build test WARNING on mtd/nand/next linus/master v6.12-rc5 next-20241030] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch#_base_tree_information] url: https://github.com/intel-lab-lkp/linux/commits/Bastien-Curutchet/memory-ti-aemif-Create-aemif_set_cs_timings/20241030-184949 base: https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl.git for-next patch link: https://lore.kernel.org/r/20241030104717.88688-3-bastien.curutchet%40bootlin.com patch subject: [PATCH 2/5] memory: ti-aemif: export aemif_set_cs_timing() config: arc-randconfig-001-20241031 (https://download.01.org/0day-ci/archive/20241031/202410311304.0fuqFK2M-lkp@intel.com/config) compiler: arc-elf-gcc (GCC) 13.2.0 reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20241031/202410311304.0fuqFK2M-lkp@intel.com/reproduce) If you fix the issue in a separate patch/commit (i.e. not just a new version of the same patch/commit), kindly add following tags | Reported-by: kernel test robot <lkp@intel.com> | Closes: https://lore.kernel.org/oe-kbuild-all/202410311304.0fuqFK2M-lkp@intel.com/ All warnings (new ones prefixed by >>): >> drivers/memory/ti-aemif.c:130: warning: Function parameter or struct member 'config_cs_lock' not described in 'aemif_device' >> drivers/memory/ti-aemif.c:130: warning: Excess struct member 'cs_config_lock' description in 'aemif_device' Kconfig warnings: (for reference only) WARNING: unmet direct dependencies detected for GET_FREE_REGION Depends on [n]: SPARSEMEM [=n] Selected by [m]: - RESOURCE_KUNIT_TEST [=m] && RUNTIME_TESTING_MENU [=y] && KUNIT [=m] vim +130 drivers/memory/ti-aemif.c 5a7c81547c1db75 Ivan Khoronzhuk 2014-02-24 111 5a7c81547c1db75 Ivan Khoronzhuk 2014-02-24 112 /** 5a7c81547c1db75 Ivan Khoronzhuk 2014-02-24 113 * struct aemif_device: structure to hold device data 5a7c81547c1db75 Ivan Khoronzhuk 2014-02-24 114 * @base: base address of AEMIF registers 5a7c81547c1db75 Ivan Khoronzhuk 2014-02-24 115 * @clk: source clock 5a7c81547c1db75 Ivan Khoronzhuk 2014-02-24 116 * @clk_rate: clock's rate in kHz 5a7c81547c1db75 Ivan Khoronzhuk 2014-02-24 117 * @num_cs: number of assigned chip-selects 5a7c81547c1db75 Ivan Khoronzhuk 2014-02-24 118 * @cs_offset: start number of cs nodes 5a7c81547c1db75 Ivan Khoronzhuk 2014-02-24 119 * @cs_data: array of chip-select settings 0f034c3604121bf Bastien Curutchet 2024-10-30 120 * @cs_config_lock: lock used to access CS configuration 5a7c81547c1db75 Ivan Khoronzhuk 2014-02-24 121 */ 5a7c81547c1db75 Ivan Khoronzhuk 2014-02-24 122 struct aemif_device { 5a7c81547c1db75 Ivan Khoronzhuk 2014-02-24 123 void __iomem *base; 5a7c81547c1db75 Ivan Khoronzhuk 2014-02-24 124 struct clk *clk; 5a7c81547c1db75 Ivan Khoronzhuk 2014-02-24 125 unsigned long clk_rate; 5a7c81547c1db75 Ivan Khoronzhuk 2014-02-24 126 u8 num_cs; 5a7c81547c1db75 Ivan Khoronzhuk 2014-02-24 127 int cs_offset; 5a7c81547c1db75 Ivan Khoronzhuk 2014-02-24 128 struct aemif_cs_data cs_data[NUM_CS]; 0f034c3604121bf Bastien Curutchet 2024-10-30 129 spinlock_t config_cs_lock; 5a7c81547c1db75 Ivan Khoronzhuk 2014-02-24 @130 }; 5a7c81547c1db75 Ivan Khoronzhuk 2014-02-24 131
diff --git a/drivers/memory/ti-aemif.c b/drivers/memory/ti-aemif.c index 5be6df246075..ee857c16a02c 100644 --- a/drivers/memory/ti-aemif.c +++ b/drivers/memory/ti-aemif.c @@ -17,6 +17,8 @@ #include <linux/of.h> #include <linux/of_platform.h> #include <linux/platform_device.h> +#include <linux/spinlock.h> +#include <memory/ti-aemif.h> #define TA_SHIFT 2 #define RHOLD_SHIFT 4 @@ -107,27 +109,6 @@ struct aemif_cs_data { u8 asize; }; -/** - * struct aemif_cs_timing: structure to hold cs timing configuration - * values are expressed in number of clock cycles - 1 - * @ta: minimum turn around time - * @rhold read hold width - * @rstrobe read strobe width - * @rsetup read setup width - * @whold write hold width - * @wstrobe write strobe width - * @wsetup write setup width - */ -struct aemif_cs_timings { - u32 ta; - u32 rhold; - u32 rstrobe; - u32 rsetup; - u32 whold; - u32 wstrobe; - u32 wsetup; -}; - /** * struct aemif_device: structure to hold device data * @base: base address of AEMIF registers @@ -136,6 +117,7 @@ struct aemif_cs_timings { * @num_cs: number of assigned chip-selects * @cs_offset: start number of cs nodes * @cs_data: array of chip-select settings + * @cs_config_lock: lock used to access CS configuration */ struct aemif_device { void __iomem *base; @@ -144,6 +126,7 @@ struct aemif_device { u8 num_cs; int cs_offset; struct aemif_cs_data cs_data[NUM_CS]; + spinlock_t config_cs_lock; }; /** @@ -154,8 +137,9 @@ struct aemif_device { * * Returns 0 on success, else negative errno. */ -static int aemif_set_cs_timings(struct aemif_device *aemif, u8 cs, struct aemif_cs_timings *timings) +int aemif_set_cs_timings(struct aemif_device *aemif, u8 cs, struct aemif_cs_timings *timings) { + unsigned long flags; unsigned int offset; u32 val, set; @@ -176,13 +160,16 @@ static int aemif_set_cs_timings(struct aemif_device *aemif, u8 cs, struct aemif_ offset = A1CR_OFFSET + cs * 4; + spin_lock_irqsave(&aemif->config_cs_lock, flags); val = readl(aemif->base + offset); val &= ~TIMINGS_MASK; val |= set; writel(val, aemif->base + offset); + spin_unlock_irqrestore(&aemif->config_cs_lock, flags); return 0; } +EXPORT_SYMBOL(aemif_set_cs_timings); /** * aemif_calc_rate - calculate timing data. @@ -231,6 +218,7 @@ static int aemif_config_abus(struct platform_device *pdev, int csnum) struct aemif_cs_data *data = &aemif->cs_data[csnum]; unsigned long clk_rate = aemif->clk_rate; struct aemif_cs_timings timings; + unsigned long flags; unsigned offset; u32 set, val; @@ -250,10 +238,12 @@ static int aemif_config_abus(struct platform_device *pdev, int csnum) if (data->enable_ss) set |= ACR_SSTROBE_MASK; + spin_lock_irqsave(&aemif->config_cs_lock, flags); val = readl(aemif->base + offset); val &= ~CONFIG_MASK; val |= set; writel(val, aemif->base + offset); + spin_unlock_irqrestore(&aemif->config_cs_lock, flags); return aemif_set_cs_timings(aemif, data->cs - aemif->cs_offset, &timings); } @@ -396,6 +386,7 @@ static int aemif_probe(struct platform_device *pdev) if (IS_ERR(aemif->base)) return PTR_ERR(aemif->base); + spin_lock_init(&aemif->config_cs_lock); if (np) { /* * For every controller device node, there is a cs device node diff --git a/include/memory/ti-aemif.h b/include/memory/ti-aemif.h new file mode 100644 index 000000000000..a1478387a8d0 --- /dev/null +++ b/include/memory/ti-aemif.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#ifndef __TI_AEMIF_H +#define __TI_AEMIF_H + +/** + * struct aemif_cs_timing: structure to hold cs timing configuration + * values are expressed in number of clock cycles - 1 + * @ta: minimum turn around time + * @rhold read hold width + * @rstrobe read strobe width + * @rsetup read setup width + * @whold write hold width + * @wstrobe write strobe width + * @wsetup write setup width + */ +struct aemif_cs_timings { + u32 ta; + u32 rhold; + u32 rstrobe; + u32 rsetup; + u32 whold; + u32 wstrobe; + u32 wsetup; +}; + +struct aemif_device; + +int aemif_set_cs_timings(struct aemif_device *aemif, u8 cs, struct aemif_cs_timings *timings); + +#endif // __TI_AEMIF_H
Export the aemif_set_cs_timing() symbol so it can be used by other drivers Add a spinlock to protect the CS configuration register from concurrent accesses. Signed-off-by: Bastien Curutchet <bastien.curutchet@bootlin.com> --- drivers/memory/ti-aemif.c | 35 +++++++++++++---------------------- include/memory/ti-aemif.h | 31 +++++++++++++++++++++++++++++++ 2 files changed, 44 insertions(+), 22 deletions(-) create mode 100644 include/memory/ti-aemif.h