| Message ID | 20240930132344.3001876-4-andrei.stefanescu@oss.nxp.com |
|---|---|
| State | New |
| Headers | show
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Mon, 30 Sep 2024 13:24:37 +0000 Received: from AM9PR04MB8487.eurprd04.prod.outlook.com ([fe80::6d7a:8d2:f020:455]) by AM9PR04MB8487.eurprd04.prod.outlook.com ([fe80::6d7a:8d2:f020:455%5]) with mapi id 15.20.7962.022; Mon, 30 Sep 2024 13:24:37 +0000 From: Andrei Stefanescu <andrei.stefanescu@oss.nxp.com> To: Dong Aisheng <aisheng.dong@nxp.com>, Fabio Estevam <festevam@gmail.com>, Shawn Guo <shawnguo@kernel.org>, Jacky Bai <ping.bai@nxp.com>, Linus Walleij <linus.walleij@linaro.org>, Rob Herring <robh@kernel.org>, Krzysztof Kozlowski <krzk+dt@kernel.org>, Conor Dooley <conor+dt@kernel.org>, Ghennadi Procopciuc <Ghennadi.Procopciuc@oss.nxp.com>, Chester Lin <chester62515@gmail.com>, Matthias Brugger <mbrugger@suse.com>, Sascha Hauer <s.hauer@pengutronix.de> Cc: Pengutronix Kernel Team <kernel@pengutronix.de>, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, imx@lists.linux.dev, NXP S32 Linux Team <s32@nxp.com>, Christophe Lizzi <clizzi@redhat.com>, Alberto Ruiz <aruizrui@redhat.com>, Enric Balletbo <eballetb@redhat.com>, Andrei Stefanescu <andrei.stefanescu@oss.nxp.com> Subject: [PATCH 3/3] arm64: dts: S32G3: add S32G3 compatible for the pinctrl node Date: Mon, 30 Sep 2024 16:23:44 +0300 Message-ID: <20240930132344.3001876-4-andrei.stefanescu@oss.nxp.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240930132344.3001876-1-andrei.stefanescu@oss.nxp.com> References: <20240930132344.3001876-1-andrei.stefanescu@oss.nxp.com> Content-Type: text/plain; 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pinctrl: s32: add missing pins and an S32G3 compatible
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On 30/09/2024 15:23, Andrei Stefanescu wrote: > Add the newly introduced S32G3 compatible for the pinctrl node. > Currently, it will fall back to the S32G2 compatible. > > Signed-off-by: Andrei Stefanescu <andrei.stefanescu@oss.nxp.com> Reviewed-by: Matthias Brugger <mbrugger@suse.com> > --- > arch/arm64/boot/dts/freescale/s32g3.dtsi | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/arch/arm64/boot/dts/freescale/s32g3.dtsi b/arch/arm64/boot/dts/freescale/s32g3.dtsi > index b4226a9143c8..f6aafe44c9d7 100644 > --- a/arch/arm64/boot/dts/freescale/s32g3.dtsi > +++ b/arch/arm64/boot/dts/freescale/s32g3.dtsi > @@ -172,7 +172,8 @@ soc@0 { > ranges = <0 0 0 0x80000000>; > > pinctrl: pinctrl@4009c240 { > - compatible = "nxp,s32g2-siul2-pinctrl"; > + compatible = "nxp,s32g3-siul2-pinctrl", > + "nxp,s32g2-siul2-pinctrl"; > /* MSCR0-MSCR101 registers on siul2_0 */ > reg = <0x4009c240 0x198>, > /* MSCR112-MSCR122 registers on siul2_1 */
diff --git a/arch/arm64/boot/dts/freescale/s32g3.dtsi b/arch/arm64/boot/dts/freescale/s32g3.dtsi index b4226a9143c8..f6aafe44c9d7 100644 --- a/arch/arm64/boot/dts/freescale/s32g3.dtsi +++ b/arch/arm64/boot/dts/freescale/s32g3.dtsi @@ -172,7 +172,8 @@ soc@0 { ranges = <0 0 0 0x80000000>; pinctrl: pinctrl@4009c240 { - compatible = "nxp,s32g2-siul2-pinctrl"; + compatible = "nxp,s32g3-siul2-pinctrl", + "nxp,s32g2-siul2-pinctrl"; /* MSCR0-MSCR101 registers on siul2_0 */ reg = <0x4009c240 0x198>, /* MSCR112-MSCR122 registers on siul2_1 */
Add the newly introduced S32G3 compatible for the pinctrl node. Currently, it will fall back to the S32G2 compatible. Signed-off-by: Andrei Stefanescu <andrei.stefanescu@oss.nxp.com> --- arch/arm64/boot/dts/freescale/s32g3.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)