From patchwork Tue Sep 30 08:45:04 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 394808 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 2D6111400A3 for ; Tue, 30 Sep 2014 18:45:40 +1000 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752695AbaI3Ipi (ORCPT ); Tue, 30 Sep 2014 04:45:38 -0400 Received: from mail-wg0-f50.google.com ([74.125.82.50]:34677 "EHLO mail-wg0-f50.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753403AbaI3IpO (ORCPT ); Tue, 30 Sep 2014 04:45:14 -0400 Received: by mail-wg0-f50.google.com with SMTP id l18so13614942wgh.21 for ; Tue, 30 Sep 2014 01:45:12 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=e1uqVXW4xBbMZj1X50i1n4cxICS5fvAoTbTpdah9RaE=; b=GmC5lX0OQRlgSs9kwDJ4FeZ5aenZdlnJw9l1XI4TH8K9FkP7M/JPEXyV6KIZwEsEg8 3oFqvRsxT8OuCALkhhOlAOgPWj4yu/Gm3DlmYigzQxtyWIsLxnYaxAQJsmnPjxgATyOT ztHbJ7k+Olhh3/GjpNprLmvkW6ilwtkj5bTd9bH8SWNZV6Eh97GrqRk10MxXXDKJsIId XUlmayUFBtI9vlr+OWUYYM+8Nx0THWOGhzdRsurNwddVsm8Swx2iNnnmRvnxEtRmBW8v rsaaftjzE3y4jDpYnpYsVtPxAcNev174j2wHQx1AMNvTR+8tydrc3sa2QvtuebW33AWp JCMA== X-Gm-Message-State: ALoCoQms+rndRhLmfwKSTHcNQaScYp7rxSkFrHcI/gTdS/vPcGWnc5SsDd6dUU7LFjtKI4Hd1oi1 X-Received: by 10.194.8.232 with SMTP id u8mr52461908wja.64.1412066712454; Tue, 30 Sep 2014 01:45:12 -0700 (PDT) Received: from localhost.localdomain ([85.235.11.236]) by mx.google.com with ESMTPSA id ba3sm14386256wib.10.2014.09.30.01.45.10 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 30 Sep 2014 01:45:11 -0700 (PDT) From: Linus Walleij To: linux-kernel@vger.kernel.org, Barry Song , Barry Song Cc: linux-gpio@vger.kernel.org, Linus Walleij Subject: [PATCH] RESEND RFT: pinctrl: sirf: move sgpio lock into state container Date: Tue, 30 Sep 2014 10:45:04 +0200 Message-Id: <1412066704-28633-1-git-send-email-linus.walleij@linaro.org> X-Mailer: git-send-email 1.9.3 Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Instead of referring to a global static variable for the sgpio locking, use the state container to contain the lock. Signed-off-by: Linus Walleij --- Barry, did you get around to testing this patch? --- drivers/pinctrl/sirf/pinctrl-sirf.c | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/drivers/pinctrl/sirf/pinctrl-sirf.c b/drivers/pinctrl/sirf/pinctrl-sirf.c index 4c1d7c68666d..3ac7848a8551 100644 --- a/drivers/pinctrl/sirf/pinctrl-sirf.c +++ b/drivers/pinctrl/sirf/pinctrl-sirf.c @@ -40,10 +40,9 @@ struct sirfsoc_gpio_chip { struct of_mm_gpio_chip chip; bool is_marco; /* for marco, some registers are different with prima2 */ struct sirfsoc_gpio_bank sgpio_bank[SIRFSOC_GPIO_NO_OF_BANKS]; + spinlock_t lock; }; -static DEFINE_SPINLOCK(sgpio_lock); - static struct sirfsoc_pin_group *sirfsoc_pin_groups; static int sirfsoc_pingrp_cnt; @@ -440,13 +439,13 @@ static void sirfsoc_gpio_irq_ack(struct irq_data *d) offset = SIRFSOC_GPIO_CTRL(bank->id, idx); - spin_lock_irqsave(&sgpio_lock, flags); + spin_lock_irqsave(&sgpio->lock, flags); val = readl(sgpio->chip.regs + offset); writel(val, sgpio->chip.regs + offset); - spin_unlock_irqrestore(&sgpio_lock, flags); + spin_unlock_irqrestore(&sgpio->lock, flags); } static void __sirfsoc_gpio_irq_mask(struct sirfsoc_gpio_chip *sgpio, @@ -458,14 +457,14 @@ static void __sirfsoc_gpio_irq_mask(struct sirfsoc_gpio_chip *sgpio, offset = SIRFSOC_GPIO_CTRL(bank->id, idx); - spin_lock_irqsave(&sgpio_lock, flags); + spin_lock_irqsave(&sgpio->lock, flags); val = readl(sgpio->chip.regs + offset); val &= ~SIRFSOC_GPIO_CTL_INTR_EN_MASK; val &= ~SIRFSOC_GPIO_CTL_INTR_STS_MASK; writel(val, sgpio->chip.regs + offset); - spin_unlock_irqrestore(&sgpio_lock, flags); + spin_unlock_irqrestore(&sgpio->lock, flags); } static void sirfsoc_gpio_irq_mask(struct irq_data *d) @@ -488,14 +487,14 @@ static void sirfsoc_gpio_irq_unmask(struct irq_data *d) offset = SIRFSOC_GPIO_CTRL(bank->id, idx); - spin_lock_irqsave(&sgpio_lock, flags); + spin_lock_irqsave(&sgpio->lock, flags); val = readl(sgpio->chip.regs + offset); val &= ~SIRFSOC_GPIO_CTL_INTR_STS_MASK; val |= SIRFSOC_GPIO_CTL_INTR_EN_MASK; writel(val, sgpio->chip.regs + offset); - spin_unlock_irqrestore(&sgpio_lock, flags); + spin_unlock_irqrestore(&sgpio->lock, flags); } static int sirfsoc_gpio_irq_type(struct irq_data *d, unsigned type) @@ -509,7 +508,7 @@ static int sirfsoc_gpio_irq_type(struct irq_data *d, unsigned type) offset = SIRFSOC_GPIO_CTRL(bank->id, idx); - spin_lock_irqsave(&sgpio_lock, flags); + spin_lock_irqsave(&sgpio->lock, flags); val = readl(sgpio->chip.regs + offset); val &= ~(SIRFSOC_GPIO_CTL_INTR_STS_MASK | SIRFSOC_GPIO_CTL_OUT_EN_MASK); @@ -541,7 +540,7 @@ static int sirfsoc_gpio_irq_type(struct irq_data *d, unsigned type) writel(val, sgpio->chip.regs + offset); - spin_unlock_irqrestore(&sgpio_lock, flags); + spin_unlock_irqrestore(&sgpio->lock, flags); return 0; } @@ -704,11 +703,11 @@ static int sirfsoc_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, offset = SIRFSOC_GPIO_CTRL(bank->id, idx); - spin_lock_irqsave(&sgpio_lock, flags); + spin_lock_irqsave(&sgpio->lock, flags); sirfsoc_gpio_set_output(sgpio, bank, offset, value); - spin_unlock_irqrestore(&sgpio_lock, flags); + spin_unlock_irqrestore(&sgpio->lock, flags); return 0; } @@ -801,6 +800,7 @@ static int sirfsoc_gpio_probe(struct device_node *np) sgpio = devm_kzalloc(&pdev->dev, sizeof(*sgpio), GFP_KERNEL); if (!sgpio) return -ENOMEM; + spin_lock_init(&sgpio->lock); regs = of_iomap(np, 0); if (!regs)