diff mbox series

[v1,3/8] ARM: dts: aspeed: system1: Add RGMII support

Message ID 20241213145037.3784931-4-ninad@linux.ibm.com
State New
Headers show
Series DTS updates for system1 BMC | expand

Commit Message

Ninad Palsule Dec. 13, 2024, 2:50 p.m. UTC
From: NINAD PALSULE <ninadpalsule@us.ibm.com>

system1 has 2 transceiver connected through the RGMII interfaces. Added
device tree entry to enable RGMII support.

Signed-off-by: Ninad Palsule <ninad@linux.ibm.com>
---
 .../dts/aspeed/aspeed-bmc-ibm-system1.dts     | 38 ++++++++++++++++---
 1 file changed, 33 insertions(+), 5 deletions(-)

Comments

Andrew Lunn Dec. 13, 2024, 10:03 p.m. UTC | #1
> +&mac0 {
> +	status = "okay";
> +
> +	phy-mode = "rgmii-rxid";

Why is everybody getting RGMII wrong this week?

Do you have an extra long clock line on the PCB for the TX clock?

> +	phy-handle = <&ethphy0>;
> +
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_rgmii1_default>;
> +};
> +
>  &mac2 {
>  	status = "okay";
> +
> +	phy-mode = "rgmii";

Do you have extra long clock lines on the PCB for both Rx and Tx
clock?

I suspect you don't and the RGMII delays are messed up somehow.

	Andrew
Ninad Palsule Jan. 7, 2025, 2:26 p.m. UTC | #2
Hi Andrew,

Thank you for the review. Sorry for the late reply as I was on vacation.

On 12/13/24 16:03, Andrew Lunn wrote:
>> +&mac0 {
>> +	status = "okay";
>> +
>> +	phy-mode = "rgmii-rxid";
> Why is everybody getting RGMII wrong this week?
>
> Do you have an extra long clock line on the PCB for the TX clock?

We are using ASPEED ast2600 chip and their recommendation is to enable 
RX interface delay from the PHY chip for mac0 and mac1.

We tested the network and it is working as expected.

>
>> +	phy-handle = <&ethphy0>;
>> +
>> +	pinctrl-names = "default";
>> +	pinctrl-0 = <&pinctrl_rgmii1_default>;
>> +};
>> +
>>   &mac2 {
>>   	status = "okay";
>> +
>> +	phy-mode = "rgmii";
> Do you have extra long clock lines on the PCB for both Rx and Tx
> clock?
>
> I suspect you don't and the RGMII delays are messed up somehow.

This is a recommendation by ASPEED for mac2 and mac3. We tested the 
network and it is working as expected.

Can you please let me know more about your concern?

Regards,

Ninad

>
> 	Andrew
>
diff mbox series

Patch

diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-system1.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-system1.dts
index db4b9fb674fe..775a95470f5c 100644
--- a/arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-system1.dts
+++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-system1.dts
@@ -425,14 +425,42 @@  &lpc_ctrl {
 	memory-region = <&flash_memory>;
 };
 
+&mdio0 {
+	status = "okay";
+
+	ethphy0: ethernet-phy@0 {
+		compatible = "ethernet-phy-ieee802.3-c22";
+		reg = <0>;
+	};
+};
+
+&mdio2 {
+	status = "okay";
+
+	ethphy2: ethernet-phy@0 {
+		compatible = "ethernet-phy-ieee802.3-c22";
+		reg = <0>;
+	};
+};
+
+&mac0 {
+	status = "okay";
+
+	phy-mode = "rgmii-rxid";
+	phy-handle = <&ethphy0>;
+
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_rgmii1_default>;
+};
+
 &mac2 {
 	status = "okay";
+
+	phy-mode = "rgmii";
+	phy-handle = <&ethphy2>;
+
 	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_rmii3_default>;
-	clocks = <&syscon ASPEED_CLK_GATE_MAC3CLK>,
-		 <&syscon ASPEED_CLK_MAC3RCLK>;
-	clock-names = "MACCLK", "RCLK";
-	use-ncsi;
+	pinctrl-0 = <&pinctrl_rgmii3_default>;
 };
 
 &mac3 {