| Message ID | 20210812233753.104217-14-vgupta@kernel.org |
|---|---|
| State | New |
| Headers | show |
| Series | ARC mm updates: support 3/4 levels and asm-generic/pgalloc | expand |
Hi Vineet,
I love your patch! Yet something to improve:
[auto build test ERROR on arc/for-next]
[also build test ERROR on next-20210812]
[cannot apply to linux/master linus/master v5.14-rc5]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Vineet-Gupta/ARC-mm-updates-support-3-4-levels-and-asm-generic-pgalloc/20210813-074023
base: https://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc.git for-next
config: arc-allyesconfig (attached as .config)
compiler: arceb-elf-gcc (GCC) 10.3.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/0day-ci/linux/commit/0411d3a95cb73722d026f7b3d9c9d8abab8c0d79
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Vineet-Gupta/ARC-mm-updates-support-3-4-levels-and-asm-generic-pgalloc/20210813-074023
git checkout 0411d3a95cb73722d026f7b3d9c9d8abab8c0d79
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-10.3.0 make.cross ARCH=arc
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All errors (new ones prefixed by >>):
In file included from arch/arc/include/asm/mmu.h:19,
from include/linux/mm_types.h:19,
from include/linux/buildid.h:5,
from include/linux/module.h:14,
from lib/test_bitops.c:9:
>> arch/arc/include/asm/mmu-arcv2.h:80:1: error: 'inline' is not at beginning of declaration [-Werror=old-style-declaration]
80 | static void inline mmu_setup_asid(struct mm_struct *mm, unsigned long asid)
| ^~~~~~
arch/arc/include/asm/mmu-arcv2.h:85:1: error: 'inline' is not at beginning of declaration [-Werror=old-style-declaration]
85 | static void inline mmu_setup_pgd(struct mm_struct *mm, void *pgd)
| ^~~~~~
cc1: all warnings being treated as errors
vim +/inline +80 arch/arc/include/asm/mmu-arcv2.h
79
> 80 static void inline mmu_setup_asid(struct mm_struct *mm, unsigned long asid)
81 {
82 write_aux_reg(ARC_REG_PID, asid | MMU_ENABLE);
83 }
84
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
On 8/12/21 9:01 PM, kernel test robot wrote: > Hi Vineet, > > I love your patch! Yet something to improve: > > [auto build test ERROR on arc/for-next] > [also build test ERROR on next-20210812] > [cannot apply to linux/master linus/master v5.14-rc5] > [If your patch is applied to the wrong git tree, kindly drop us a note. > And when submitting patch, we suggest to use '--base' as documented in > https://git-scm.com/docs/git-format-patch] > > url:https://github.com/0day-ci/linux/commits/Vineet-Gupta/ARC-mm-updates-support-3-4-levels-and-asm-generic-pgalloc/20210813-074023 > base:https://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc.git for-next > config: arc-allyesconfig (attached as .config) > compiler: arceb-elf-gcc (GCC) 10.3.0 > reproduce (this is a W=1 build): > wgethttps://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross > chmod +x ~/bin/make.cross > #https://github.com/0day-ci/linux/commit/0411d3a95cb73722d026f7b3d9c9d8abab8c0d79 > git remote add linux-reviewhttps://github.com/0day-ci/linux > git fetch --no-tags linux-review Vineet-Gupta/ARC-mm-updates-support-3-4-levels-and-asm-generic-pgalloc/20210813-074023 > git checkout 0411d3a95cb73722d026f7b3d9c9d8abab8c0d79 > # save the attached .config to linux build tree > COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-10.3.0 make.cross ARCH=arc > > If you fix the issue, kindly add following tag as appropriate > Reported-by: kernel test robot<lkp@intel.com> > > All errors (new ones prefixed by >>): > > In file included from arch/arc/include/asm/mmu.h:19, > from include/linux/mm_types.h:19, > from include/linux/buildid.h:5, > from include/linux/module.h:14, > from lib/test_bitops.c:9: >>> arch/arc/include/asm/mmu-arcv2.h:80:1: error: 'inline' is not at beginning of declaration [-Werror=old-style-declaration] > 80 | static void inline mmu_setup_asid(struct mm_struct *mm, unsigned long asid) > | ^~~~~~ > arch/arc/include/asm/mmu-arcv2.h:85:1: error: 'inline' is not at beginning of declaration [-Werror=old-style-declaration] > 85 | static void inline mmu_setup_pgd(struct mm_struct *mm, void *pgd) > | ^~~~~~ > cc1: all warnings being treated as errors Strange my gcc11 is not tripping on this snafu. Fixed now. Thx for the report as always. -Vineet
diff --git a/arch/arc/include/asm/mmu-arcv2.h b/arch/arc/include/asm/mmu-arcv2.h new file mode 100644 index 000000000000..4c47dd3864d1 --- /dev/null +++ b/arch/arc/include/asm/mmu-arcv2.h @@ -0,0 +1,103 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2004, 2007-2010, 2011-2012, 2019-20 Synopsys, Inc. (www.synopsys.com) + * + * MMUv3 (arc700) / MMUv4 (archs) are software page walked and software managed. + * This file contains the TLB access registers and commands + */ + +#ifndef _ASM_ARC_MMU_ARCV2_H +#define _ASM_ARC_MMU_ARCV2_H + +/* + * TLB Management regs + */ +#define ARC_REG_MMU_BCR 0x06f + +#ifdef CONFIG_ARC_MMU_V3 +#define ARC_REG_TLBPD0 0x405 +#define ARC_REG_TLBPD1 0x406 +#define ARC_REG_TLBPD1HI 0 /* Dummy: allows common code */ +#define ARC_REG_TLBINDEX 0x407 +#define ARC_REG_TLBCOMMAND 0x408 +#define ARC_REG_PID 0x409 +#define ARC_REG_SCRATCH_DATA0 0x418 +#else +#define ARC_REG_TLBPD0 0x460 +#define ARC_REG_TLBPD1 0x461 +#define ARC_REG_TLBPD1HI 0x463 +#define ARC_REG_TLBINDEX 0x464 +#define ARC_REG_TLBCOMMAND 0x465 +#define ARC_REG_PID 0x468 +#define ARC_REG_SCRATCH_DATA0 0x46c +#endif + +/* Bits in MMU PID reg */ +#define __TLB_ENABLE (1 << 31) +#define __PROG_ENABLE (1 << 30) +#define MMU_ENABLE (__TLB_ENABLE | __PROG_ENABLE) + +/* Bits in TLB Index reg */ +#define TLB_LKUP_ERR 0x80000000 + +#ifdef CONFIG_ARC_MMU_V3 +#define TLB_DUP_ERR (TLB_LKUP_ERR | 0x00000001) +#else +#define TLB_DUP_ERR (TLB_LKUP_ERR | 0x40000000) +#endif + +/* + * TLB Commands + */ +#define TLBWrite 0x1 +#define TLBRead 0x2 +#define TLBGetIndex 0x3 +#define TLBProbe 0x4 +#define TLBWriteNI 0x5 /* write JTLB without inv uTLBs */ +#define TLBIVUTLB 0x6 /* explicitly inv uTLBs */ + +#ifdef CONFIG_ARC_MMU_V4 +#define TLBInsertEntry 0x7 +#define TLBDeleteEntry 0x8 +#endif + +/* Masks for actual TLB "PD"s */ +#define PTE_BITS_IN_PD0 (_PAGE_GLOBAL | _PAGE_PRESENT | _PAGE_HW_SZ) +#define PTE_BITS_RWX (_PAGE_EXECUTE | _PAGE_WRITE | _PAGE_READ) + +#define PTE_BITS_NON_RWX_IN_PD1 (PAGE_MASK_PHYS | _PAGE_CACHEABLE) + +#ifndef __ASSEMBLY__ + +struct mm_struct; +extern int pae40_exist_but_not_enab(void); + +static inline int is_pae40_enabled(void) +{ + return IS_ENABLED(CONFIG_ARC_HAS_PAE40); +} + +static void inline mmu_setup_asid(struct mm_struct *mm, unsigned long asid) +{ + write_aux_reg(ARC_REG_PID, asid | MMU_ENABLE); +} + +static void inline mmu_setup_pgd(struct mm_struct *mm, void *pgd) +{ + /* PGD cached in MMU reg to avoid 3 mem lookups: task->mm->pgd */ +#ifdef CONFIG_ISA_ARCV2 + write_aux_reg(ARC_REG_SCRATCH_DATA0, (unsigned int)pgd); +#endif +} + +#else + +.macro ARC_MMU_REENABLE reg + lr \reg, [ARC_REG_PID] + or \reg, \reg, MMU_ENABLE + sr \reg, [ARC_REG_PID] +.endm + +#endif /* !__ASSEMBLY__ */ + +#endif diff --git a/arch/arc/include/asm/mmu.h b/arch/arc/include/asm/mmu.h index 414a27e806b6..ca427c30f70e 100644 --- a/arch/arc/include/asm/mmu.h +++ b/arch/arc/include/asm/mmu.h @@ -7,91 +7,15 @@ #define _ASM_ARC_MMU_H #ifndef __ASSEMBLY__ -#include <linux/threads.h> /* NR_CPUS */ -#endif - -/* MMU Management regs */ -#define ARC_REG_MMU_BCR 0x06f - -#ifdef CONFIG_ARC_MMU_V3 -#define ARC_REG_TLBPD0 0x405 -#define ARC_REG_TLBPD1 0x406 -#define ARC_REG_TLBPD1HI 0 /* Dummy: allows code sharing with ARC700 */ -#define ARC_REG_TLBINDEX 0x407 -#define ARC_REG_TLBCOMMAND 0x408 -#define ARC_REG_PID 0x409 -#define ARC_REG_SCRATCH_DATA0 0x418 -#else -#define ARC_REG_TLBPD0 0x460 -#define ARC_REG_TLBPD1 0x461 -#define ARC_REG_TLBPD1HI 0x463 -#define ARC_REG_TLBINDEX 0x464 -#define ARC_REG_TLBCOMMAND 0x465 -#define ARC_REG_PID 0x468 -#define ARC_REG_SCRATCH_DATA0 0x46c -#endif - -/* Bits in MMU PID register */ -#define __TLB_ENABLE (1 << 31) -#define __PROG_ENABLE (1 << 30) -#define MMU_ENABLE (__TLB_ENABLE | __PROG_ENABLE) - -/* Error code if probe fails */ -#define TLB_LKUP_ERR 0x80000000 - -#ifdef CONFIG_ARC_MMU_V3 -#define TLB_DUP_ERR (TLB_LKUP_ERR | 0x00000001) -#else -#define TLB_DUP_ERR (TLB_LKUP_ERR | 0x40000000) -#endif - -/* TLB Commands */ -#define TLBWrite 0x1 -#define TLBRead 0x2 -#define TLBGetIndex 0x3 -#define TLBProbe 0x4 -#define TLBWriteNI 0x5 /* write JTLB without inv uTLBs */ -#define TLBIVUTLB 0x6 /* explicitly inv uTLBs */ -#ifdef CONFIG_ARC_MMU_V4 -#define TLBInsertEntry 0x7 -#define TLBDeleteEntry 0x8 -#endif - -#ifndef __ASSEMBLY__ +#include <linux/threads.h> /* NR_CPUS */ typedef struct { unsigned long asid[NR_CPUS]; /* 8 bit MMU PID + Generation cycle */ } mm_context_t; -static void inline mmu_setup_asid(struct mm_struct *mm, unsigned int asid) -{ - write_aux_reg(ARC_REG_PID, asid | MMU_ENABLE); -} - -static void inline mmu_setup_pgd(struct mm_struct *mm, void *pgd) -{ - /* PGD cached in MMU reg to avoid 3 mem lookups: task->mm->pgd */ -#ifdef CONFIG_ISA_ARCV2 - write_aux_reg(ARC_REG_SCRATCH_DATA0, (unsigned int)pgd); #endif -} - -static inline int is_pae40_enabled(void) -{ - return IS_ENABLED(CONFIG_ARC_HAS_PAE40); -} - -extern int pae40_exist_but_not_enab(void); - -#else - -.macro ARC_MMU_REENABLE reg - lr \reg, [ARC_REG_PID] - or \reg, \reg, MMU_ENABLE - sr \reg, [ARC_REG_PID] -.endm -#endif /* !__ASSEMBLY__ */ +#include <asm/mmu-arcv2.h> #endif diff --git a/arch/arc/include/asm/pgtable.h b/arch/arc/include/asm/pgtable.h index f762bacb2358..de4576e8d17a 100644 --- a/arch/arc/include/asm/pgtable.h +++ b/arch/arc/include/asm/pgtable.h @@ -103,12 +103,6 @@ */ #define PAGE_KERNEL __pgprot(_K_PAGE_PERMS | _PAGE_CACHEABLE) -/* Masks for actual TLB "PD"s */ -#define PTE_BITS_IN_PD0 (_PAGE_GLOBAL | _PAGE_PRESENT | _PAGE_HW_SZ) -#define PTE_BITS_RWX (_PAGE_EXECUTE | _PAGE_WRITE | _PAGE_READ) - -#define PTE_BITS_NON_RWX_IN_PD1 (PAGE_MASK_PHYS | _PAGE_CACHEABLE) - /************************************************************************** * Mapping of vm_flags (Generic VM) to PTE flags (arch specific) *
non functional change Signed-off-by: Vineet Gupta <vgupta@kernel.org> --- arch/arc/include/asm/mmu-arcv2.h | 103 +++++++++++++++++++++++++++++++ arch/arc/include/asm/mmu.h | 80 +----------------------- arch/arc/include/asm/pgtable.h | 6 -- 3 files changed, 105 insertions(+), 84 deletions(-) create mode 100644 arch/arc/include/asm/mmu-arcv2.h